x4043s8izt2 Intersil Corporation, x4043s8izt2 Datasheet
x4043s8izt2
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x4043s8izt2 Summary of contents
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Data Sheet CPU Supervisor with 4kbit EEPROM FEATURES • Selectable watchdog timer • Low V detection and reset assertion CC —Five standard reset threshold voltages —Adjust low V reset threshold voltage using CC special programming sequence —Reset signal valid ...
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Ordering Information PART NUMBER RESET PART (ACTIVE LOW) MARKING RESET (ACTIVE HIGH) X4043S8-4.5A X4043 AL X4045S8-4.5A X4043S8Z-4.5A (Note) X4043 Z AL X4045S8Z-4.5A (Note) X4045 Z AL X4043S8I-4.5A X4043 AM X4045S8I-4.5A X4043S8IZ-4.5A (Note) X4043 Z AM X4045S8IZ-4.5A (Note) X4045 Z AM ...
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Ordering Information PART NUMBER RESET PART (ACTIVE LOW) MARKING RESET (ACTIVE HIGH) X4043S8-2.7* X4043 F X4045S8-2.7* X4043S8Z-2.7* (Note) X4043 Z F X4045S8Z-2.7* (Note) X4043S8I-2.7 X4043 G X4045S8I-2.7 X4043S8IZ-2.7 (Note) X4043 Z G X4045S8IZ-2.7 (Note) X4043M8-2.7 ADG X4045M8-2.7 X4043M8Z-2.7 (Note) DAX ...
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The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized The device features an 2-wire interface and software protocol 2 allowing operation ...
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PRINCIPLES OF OPERATION Power-on Reset Application of power to the X4043/45 activates a Power-on Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. ...
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Setting a V Voltage TRIP There are two procedures used to set the threshold voltages (V ), depending if the threshold voltage to TRIP be stored is higher or lower than the present value. For example, if the present V ...
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Figure 3. Reset V Level Sequence (V TRIP SCL SDA A0h Figure 4. Sample V Reset Circuit TRIP 4.7K RESET V TRIP Adj. 7 X4043, X4045 > 3V 15-18V, ...
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Figure 5. V Programming Sequence TRIP New V applied = CC Old V applied + | Error | CC Error < MDE Control Register The control register provides the user a mechanism for changing the block lock and watchdog timer ...
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The state of the control register can be read at any time by performing a random read at address 1FFh, using the special preamble. Only one byte is read by each register read operation. The X4043/45 resets itself after the ...
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SERIAL INTERFACE Serial Interface Conventions The device supports a bidirectional bus oriented proto- col. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer ...
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Figure 8. Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Start X4043/45 ADDRESSING Slave Address Byte Following a start condition, the master must output a slave address byte. This byte consists of several ...
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Figure 10. Byte Write Sequence Signals from the Master SDA Bus Signals from the Slave Page Write The device is capable of a page write operation initiated in the same manner as the byte write opera- tion; but ...
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Acknowledge Polling The disabling of the inputs during nonvolatile cycles can be used to take advantage of the typical 5kHz write cycle time. Once the stop condition is issued to indicate the end of the master’s byte load operation, the ...
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Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the slave address byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The ...
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Data Protection The following circuitry has been included to prevent inadvertent writes: – The WEL bit must be set to allow write operations. – The proper clock count and bit sequence is required prior to the stop bit in order ...
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ABSOLUTE MAXIMUM RATINGS Temperature under bias ................... -65°C to +135°C Storage temperature ........................ -65°C to +150°C Voltage on any pin with respect to V ...................................... -1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds) ........ ...
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CAPACITANCE (T = 25° 1.0 MHz Symbol (4) C Output capacitance (SDA, RESET/RESET) OUT (4) C Input capacitance (SCL, WP) IN Notes: (4) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT ...
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TIMING DIAGRAMS Bus Timing t F SCL t SU:STA t HD:STA SDA IN SDA OUT WP Pin Timing START SCL SDA IN t SU:WP WP Write Cycle Timing SCL th SDA 8 Bit of Last Byte Nonvolatile Write Cycle Timing ...
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Power-Up and Power-Down Timing V TRIP Volts t R RESET (X4043) RESET (X4045) RESET Output Timing Symbol V Reset trip point voltage, X4043/45-4.5A TRIP Reset trip point voltage, X4043/45 Reset trip point voltage, X4043/45-2.7A Reset trip point ...
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Watchdog Time Out For 2-Wire Interface Start SCL SDA (4043) RESET Minimum Sequence to Reset WDT SCL SDA V Set/Reset Conditions TRIP (V TRIP t TSU WP t VPS SCL 0 SDA A0h Start 20 X4043, X4045 Start Clockin (0 ...
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V Programming Specifications: V TRIP Parameter t WP Program Voltage Setup time VPS t WP Program Voltage Hold time VPH t V Level Setup time TSU TRIP t V Level Hold (stable) time THD TRIP t V Program Cycle WC ...
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PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S Pin 1 Index 0.050 (1.27) 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 22 X4043, X4045 Pin ...
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PACKAGING INFORMATION 8-Lead Miniature Small Outline Gull Wing Package Type M 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.036 (0.91) 0.032 (0.81) 0.040 ± 0.002 (1.02 ± 0.05) 0.007 (0.18) 0.005 (0.13) 23 X4043, X4045 0.118 ± ...
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... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...