x40431s14i-bx4043x Intersil Corporation, x40431s14i-bx4043x Datasheet - Page 20
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x40431s14i-bx4043x
Manufacturer Part Number
x40431s14i-bx4043x
Description
4kbit Eeprom; Triple Voltage Monitor With Integrated Cpu Supervisor
Manufacturer
Intersil Corporation
Datasheet
1.X40431S14I-BX4043X.pdf
(26 pages)
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR
V
A.C. TEST CONDITIONS
A.C. CHARACTERISTICS
Note:
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
CC
SDA
Symbol
t
t
t
t
t
t
t
HD:STA
SU:DAT
HD:DAT
SU:STO
SU:STA
= 5V
t
SU:WP
HD:WP
t
f
t
HIGH
LOW
t
t
BUF
SCL
Cb
t
AA
DH
t
t
IN
(1) Cb = total capacitance of one bus line in pF.
R
F
5V
2.06kΩ
30pF
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
WP Hold Time
Capacitive load for each bus line
RESET
WDO
20
V
CC
4.6kΩ
30pF
V
10ns
V
Standard output load
CC
CC
x 0.1 to
x 0.5
V2FAIL,
V3FAIL
X40430, X40431, X40434, X40435
V2MON, V3MON
Parameter
V
CC
4.6kΩ
30pF
x 0.9
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
20 +.1Cb
20 +.1Cb
Min
100
0.1
1.3
1.3
0.6
0.6
0.6
0.6
0.6
50
50
0
0
(1)
(1)
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
Max
400
300
300
400
0.9
May 24, 2006
Unit
FN8251.1
kHz
pF
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs