km416v4104c Samsung Semiconductor, Inc., km416v4104c Datasheet - Page 8

• Manufacturer Part Number: km416v4104c
• Description: 4m X 16bit Cmos Dynamic Ram With Extended Data Out
• Manufacturer: Samsung Semiconductor, Inc.

KM416V4004C,KM416V4104C
NOTES
KM416V40(1)04C Truth Table
10.
11.
12.
13.
14.
15.
RAS
1.
2.
3.
4.
5.
6.
7.
8.
9.
H
L
L
L
L
L
L
L
L
An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are Vih/Vil. V
times are measured between V
Measured with a load equivalent to 1 TTL load and 100pF.
Operation within the
If
Assumes that
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
t
teristics only. If
duration of the cycle. If
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either
This parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in OE controlled write
cycle and read-modify-write cycles.
Operation within the
t
These specifiecations are applied in the test mode.
In test mode read cycle, the value of
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
t
t
t
WCS
RAD
ASC
CP
CWD
t
RCD
is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.
,
,
is greater than the specified
t
is referenced to the later CAS falling edge at word read-modify-write cycle.
t
CAH
t
RWD
is greater than the specified
RCH
LCAS
are referenced to the earlier CAS falling edge.
,
or
X
H
H
H
L
L
L
L
L
t
CWD
t
t
RCD
RRH
t
WCS
and
must be satisfied for a read cycle.
t
t
RCD
t
RCD
RAD
t
t
AWD
WCS
UCAS
t
(max).
CWD
(max) limit insures that
(max) limit insures that
H
H
H
X
L
L
L
L
L
(min), the cycles is an early write cycle and the data output will remain high impedance for the
are non restrictive operating parameters. They are included in the data sheet as electric charac-
t
CWD
IH
(min) and V
t
IH
RAD
(min) and V
t
(min),
RCD
(max) limit, then access time is controlled by
t
RAC
(max) limit, then access time is controlled exclusively by
W
H
H
H
H
X
X
L
L
L
t
RWD
,
t
IL
AA
(max) and are assumed to be 2ns for all inputs.
IL
,
t
t
(max) are reference levels for measuring timing of input signals. Transition
RWD
t
RAC
t
CAC
RAC
(max) can be met.
(min) and
(max) can be met.
OE
is delayed by 2ns to 5ns for the specified values. These parameters
H
H
H
H
X
X
L
L
L
t
AWD
DQ0 - DQ7
DQ-OUT
DQ-OUT
t
DQ-IN
DQ-IN
AWD
Hi-Z
Hi-Z
Hi-Z
Hi-Z
t
RCD
-
t
RAD
(min), then the cycle is a read-modify-write cycle
(max) is specified as a reference point only.
(max) is specified as a reference point only. If
t
AA
.
DQ8-DQ15
DQ-OUT
DQ-OUT
DQ-IN
DQ-IN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
t
CAC
.
CMOS DRAM
Word Read
Word Write
Byte Read
Byte Read
Byte Write
Byte Write
Standby
Refresh
STATE
oh
-
or V
ol
.