tc90a58f TOSHIBA Semiconductor CORPORATION, tc90a58f Datasheet - Page 8

• Manufacturer Part Number: tc90a58f
• Description: 3-channel Ad Converter
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3. Y Signal Delay Circuit
4. Color Bar Generator
ROUT[7:0]
GOUT[7:0]
BOUT[7:0]
ROUT[7:0]
GOUT[7:0]
BOUT[7:0]
(4)
(5)
(6)
(7)
(8)
8- or 16-bit) Mode.
The circuit can delay the Y signal by 0 to 14 clocks in relation to the C signal.
The delay can be set in the bits YDLY3~YDLY0 of the I
Color bars for both NTSC and PAL can only be generated internally in ITU-R656 or ITU-R601 (either
The color bar mode can be set in the BAR bit of the I
ROUT[7:0]
GOUT[7:6]
GOUT[5:4]
GOUT[3:0]
BOUT[7]
BOUT[6:0]
ROUT[7:0]
GOUT[7:6]
GOUT[5:4]
GOUT[3:0]
BOUT[7]
BOUT[6:0]
Output format in Standard 4:4:1 Mode
Output format in Special 4:1:1 Mode
Note1: In the above format, 1-data cycle is the main clock (MCK).
Output format in ITU-R601 16-Bit Mode (data rate: 13.5 MHz)
Output format in ITU-R601 8-Bit Mode (data rate: 27 MHz)
ITU-R656
Adds SAV and EAV (H, V and F information) to the data in format 7 and outputs the result.
(For example, when the clock generated by HPLL is 29.82 MHz, MCK = 29.82 MHz)
Cb0
Cb0
Y0
7-0
7-0
7-0
Cb0
Cb0
Cb0
Cr0
Y0
Y0
7-0
7-0
7-6
7-6
3-2
1-0
Cr0
Y1
Y0
7-0
7-0
7-0
Cb0
Cb0
Cb0
Cr0
Y1
Y1
7-0
7-0
5-4
5-4
7-6
5-4
Cb2
Cr0
Y2
7-0
7-0
7-0
Cb0
Cr0
Cr2
Cr2
Y2
Y2
7-0
7-0
3-2
3-2
1-0
3-2
Cr2
Y3
Y1
8
7-0
7-0
7-0
Cb0
Cr0
Cr2
Cr2
Y3
Y3
2
TRG
TRG
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
C bus register Sub-Address 2AH.
7-0
7-0
1-0
7-6
5-4
2
1-0
C bus register Sub-Address 17H.
Cb4
Cb2
Y4
7-0
7-0
7-0
Cb4
Cb4
Cb4
Cr4
Y4
Y4
7-0
7-0
7-6
7-6
3-2
1-0
Cr4
Y5
Y2
7-0
7-0
7-0
Cb4
Cb4
Cb4
Cr4
Y5
Y5
7-0
7-0
5-4
5-4
7-6
5-4
Cb6
Cr2
Y6
7-0
7-0
7-0
Cb4
Cb6
Cb6
Cr4
Y6
Y6
7-0
7-0
3-2
3-2
3-2
1-0
TC90A58F
2002-02-06
Cr6
Y7
Y3
7-0
7-0
7-0