ht83f02 Holtek Semiconductor Inc., ht83f02 Datasheet
ht83f02
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ht83f02 Summary of contents
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... A full choice of HXT, ERC and HIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. The MCU flash voice memory capacity determine by user, into which the user can download their voice data. 1 HT83F02 November 19, 2010 ...
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... Block Diagram The following block diagram illustrates the main functional blocks. Pin Assignment Rev. 1.20 2 November 19, 2010 HT83F02 ...
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... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.20 Description +5.5V Storage Temperature .......................... +125 C SS +0.3V Operating Temperature......................... + Total............................................................ 100mA OH 3 HT83F02 November 19, 2010 ...
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... No load, f =12MHz, H WDT enable load, system HALT, WDT enable, f =12MHz SYS load, system HALT, WDT disable, f =12MHz SYS =0. 3.5 V =0. 8 =0. 125 4 HT83F02 Ta=25 C Typ. Max. Unit 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 0.8 1.5 mA 2.5 4.0 mA 1.0 2.0 mA 2.3 4.5 mA 1.1 2.5 mA 2.7 5.5 mA 0.7 1 ...
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... Conditions =0. =0. =0. LVR 2.4V option 2.28 LVR 2.7V option 2.565 5 HT83F02 Typ. Max. Unit mA 55 115 mA 1.0 V 2.0 V 1.9 V 3.0 V 1.4 V 2.8 V 2.1 V 3.7 V 1.1 V 2.2 V 1.9 V 3.0 V 1.3 V 2.5 V 1 100 k 30 ...
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... Conditions DD 2.4V~ 2 5.5V 2.7V~ 2 5.5V 3.3V~ 2 5.5V Ta=25 C, -2% 5V Typ. External R =120k ERC -2% 3V/5V Ta=25 C Typ =XTAL SYS f =ERC or HIRC OSC SYS 1 7 320 15 6 HT83F02 Ta=25 C Typ. Max. Unit 8 MHz 10 MHz 12 MHz 2% 8 MHz Typ MHz Typ 1024 SYS t 15~16 SYS t SYS 8 s 840 1200 s ...
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... VDD raising rate to Ensure RR VDD Power-on Reset Minimum Time for VDD Stays at t POR V to Ensure Power-on Reset POR Characteristics Curves R vs. F (External RC) Chart Characteristics Curve at 25°C Rev. 1.20 Test Conditions Min. V Conditions DD 0.035 1 7 HT83F02 Typ. Max. Unit 100 mV V/ms ms November 19, 2010 ...
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... T vs. F (External RC) Chart Characteristics Curve V vs. F (HIRC) Chart Characteristics Curve at 25°C - Trimmed at 5V Rev. 1.20 8 November 19, 2010 HT83F02 ...
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... V vs. F (HIRC) Chart Characteristics Curve at 25°C - Trimmed at 3V Rev. 1.20 9 November 19, 2010 HT83F02 ...
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... The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. System Clocking and Pipelining Instruction Fetching 10 HT83F02 November 19, 2010 ...
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... Program Counter + Program Counter S10~S0: Stack register bits @7~@0: PCL bits 11 HT83F02 * ...
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... SPI interface, the program will jump to this location and begin execution if the inter- rupt is enabled and the stack is not full. Program Memory Structure 12 November 19, 2010 HT83F02 2 C inter inter- ...
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... TBLH : : org 700h ; sets initial address of HT83F02 last page dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Rev. 1.20 The following diagram illustrates the addressing/data flow of the look-up table ...
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... Table Location P10~P8: Write P12~P8 to TBHP pointer register Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance of * must be less than 1nF. Programmer Pin RES DATA CLK Programmer and MCU Pins 14 HT83F02 * MCU Pins ...
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... Special Function Registers To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as Special Purpose Data Memory Structure 15 November 19, 2010 HT83F02 ...
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... When any operation to the relevant Indirect Addressing Regis- ters is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. 16 November 19, 2010 HT83F02 ...
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... In addition, on entering an interrupt sequence or execut- ing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. 17 November 19, 2010 HT83F02 ...
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... I/O control reg- isters during normal program operation is a useful fea- ture of these devices. Port C Pull-high Control Register - PCPHC Port C pull-high control register, PCPHC, is used to set the Port C pull high function. Port C Pull-High Control Register 18 HT83F02 November 19, 2010 ...
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... I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. 19 November 19, 2010 HT83F02 ...
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... I/O pins. Note also that the specified pins refer to the largest device package, therefore not all pins specified will exist on all devices. 20 HT83F02 November 19, 2010 ...
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... Note also that when the timer registers are read, the timer clock will be blocked to avoid errors, however, as this may result in certain timing errors, pro- grammers must take this into account. 8-bit Timer Structure 21 HT83F02 November 19, 2010 ...
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... After the timer has been initialized the timer can be turned on and off by controlling the en- able bit in the timer control register. Timer Mode Timing Diagram 22 HT83F02 November 19, 2010 ...
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... The timer can be turned off in a similar way by clearing the same bit. This example program sets the timer the timer mode which uses the internal fsys as their clock source, and produce a timer 0 interrupt per 1ms. #include HT83F02.inc jmp begin : org 04h ...
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... SYS value of 1024 this divided signal that generates the internal interrupt. The Time Base Interrupt is enabled by the ETBI bit in the INTC register and interrupt request #include HT83F02.inc jmp begin : org 04h ; time base vector jmp time_base_int ...
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... WCOL bit enabled or disabled CSEN bit enabled or disabled The status of the SPI interface pins is determined by a number of factors, whether the device is in master or slave mode and upon the condition of cer- tain control bits such as CSEN and SIMEN. Block Diagram 25 HT83F02 2 C November 19, 2010 ...
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... SIMDR register will be transmitted and any data on the SDI A/B pin will be shifted into the SIMDR A/B reg- ister. The master should output an SCS A/B signal be- fore a clock signal is provided and slave data transfers should be enabled/disabled before/after an SCS A/B signal is received. 26 HT83F02 SCS line=1 (CSEN= ...
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... Rev. 1.20 SPI Master Mode Timing SPI Slave Mode Timing - CKEG=0 SPI Slave Mode Timing - CKEG=1 27 HT83F02 November 19, 2010 ...
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... Rev. 1.20 SPI Control Register - SIMC0A/B SPI Control Register - SIMC2A/B 28 HT83F02 November 19, 2010 ...
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... Rev. 1.20 SPI Transfer Control Flowchart 29 HT83F02 November 19, 2010 ...
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... The debounce time if selected can be chosen to be either system clocks Control Register - SIMC0A HT83F02 2 C bus. Before the 2 C bus, the actual 2 C bus must bus, sends out an ...
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... RXAKA/B bit is set When this oc- curs, the transmitter will release the SDAA/B line to allow the master to send a STOP signal to release the bus. 31 HT83F02 2 C bus. When the 2 C running clock from 2 ...
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... SIMDR register the receive mode where it must implement a dummy read from the SIMDR regis- ter to release the SCL line. 32 HT83F02 2 C bus and not by the 2 C bus. To deter- November 19, 2010 ...
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... RXAK bit in the SIMC1 register to determine send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. 33 HT83F02 2 C bus. The corresponding data November 19, 2010 ...
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... Rev. 1. Bus ISR Flow Chart Bus Initialisation Flow Chart 34 HT83F02 November 19, 2010 ...
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... EMI bit should be set after entering the rou- tine, to allow interrupt nesting. If the stack is full, the in- terrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. Interrupt Control Register 35 HT83F02 November 19, 2010 ...
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... Time Base interrupt vector will 3 occur. The corresponding Program Memory vector loca- 4 tions for the Time Base is 04H. After entering the inter- rupt execution routine, the corresponding interrupt 5 request flag, TBF will be reset and the EMI bit will be cleared to disable other interrupts. 36 HT83F02 November 19, 2010 ...
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... Power Down Mode. Only the Program Counter is pushed onto the stack. If the con- tents of the register or status register are altered by the interrupt service program, which may corrupt the de- sired control sequence, then the contents should be saved in advance. 37 HT83F02 2 C inter interrupt oc- November 19, 2010 ...
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... RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initi- ated from this point. RES Reset Timing Chart 38 November 19, 2010 HT83F02 ...
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... All interrupts will be disabled Clear after reset, WDT begins WDT counting Timer All Timer will be turned off The Timer Prescaler will be Prescaler cleared Input/Output Ports I/O ports will be setup as inputs Stack Pointer will point to the top Stack Pointer of the stack 39 November 19, 2010 HT83F02 ...
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... HT83F02 WDT Time-out from HALT ...
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... Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option. 41 HT83F02 refer to the Holtek website for OSC November 19, 2010 ...
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... If the wake-up results in the execution of the next instruction following the HALT instruction, this will be executed immediately after the 1024 system clock period delay has ended. 42 November 19, 2010 HT83F02 ...
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... CLR WDT2 instruction will clear the WDT. Similarly, after the CLR WDT2 instruc- tion has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer. 43 November 19, 2010 HT83F02 ...
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... There are 8 levels of volume which are setup using the VOL register. Only the lowest 3-bits of this register are used for volume control. Rev. 1.00 Watchdog Timer Register Watchdog Timer VOL[2:0] 111 110 101 100 011 010 001 000 44 HT83F02 DAC Volume Control High Volume Low Volume August 31, 2010 ...
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... PWMCC bit changes from high to low, at the end of the duty cycle, the PWM output will stop. Pulse Width Modulator Control Register Rev. 1.20 V[3:0] PWM Volume Control 1xxx High Volume 0111 0110 0101 0100 0011 0010 0001 Low Volume 0000 45 November 19, 2010 HT83F02 ...
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... CA RNIC: enable or disable debounce time: 0/1/2 system clocks SIMB Options 17 SIMB Function: enable or disable 18 SPIB S/W CSEN: enable or disable 19 SPIB S/W WCOL: enable or disable RNIC: enable or disable debounce time: 0/1/2 system clocks Rev. 1.20 Options 2 C I/O per bit 46 November 19, 2010 HT83F02 ...
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... PA2 PA3 PA4 PA5 PA6 PA7 HT83F02 V33 V33 U14 SCLK R10 VCC SI 47K ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 48 November 19, 2010 HT83F02 ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 49 HT83F02 Cycles Flag Affected AC, OV Note AC AC ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.20 Description 50 HT83F02 Cycles Flag Affected 1 None Note 1 ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.20 51 November 19, 2010 HT83F02 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.20 addr 52 HT83F02 November 19, 2010 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT83F02 November 19, 2010 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.20 addr 54 HT83F02 November 19, 2010 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.20 Stack Stack Stack [m]. 0~6) 55 HT83F02 November 19, 2010 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.20 [m]. 0~6) 56 HT83F02 November 19, 2010 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.20 [ HT83F02 November 19, 2010 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.20 0 [m] [ HT83F02 November 19, 2010 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.20 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 59 HT83F02 November 19, 2010 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.20 60 November 19, 2010 HT83F02 ...
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... Symbol Rev. 1.20 Dimensions in inch Min. Nom. 0.228 0.150 0.008 0.386 0.054 0.025 0.004 0.022 0.007 0 Dimensions in mm Min. Nom. 5.79 3.81 0.20 9.80 1.37 0.64 0.10 0.56 0. HT83F02 Max. 0.244 0.157 0.012 0.394 0.060 0.010 0.028 0.010 8 Max. 6.20 3.99 0.30 10.01 1.52 0.25 0.71 0.25 8 November 19, 2010 ...
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... Product Tape and Reel Specifications Reel Dimensions SSOP 28S (150mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.20 Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.8 22.2 0.2 62 November 19, 2010 HT83F02 ...
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... Description W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.20 Dimensions in mm 16.0 0.3 8.0 0.1 1.75 0.1 7.5 0.1 +0.10/-0.00 1.55 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 6.5 0.1 10.3 0.1 2.1 0.1 0.30 0.05 13.3 0.1 63 November 19, 2010 HT83F02 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 64 November 19, 2010 HT83F02 ...