ep7312 Cirrus Logic, Inc., ep7312 Datasheet - Page 25

no-image

ep7312

Manufacturer Part Number
ep7312
Description
High-performance, Low-power, System-on-chip With Sdram & Enhanced Digital Audio Interface
Manufacturer
Cirrus Logic, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP7312
Manufacturer:
ALTERA
0
Part Number:
ep7312-CB
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
ep7312-CB
Manufacturer:
ST
0
Part Number:
ep7312-CBZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
ep7312-CBZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
ep7312-CR
Manufacturer:
NEC
Quantity:
12 000
Part Number:
ep7312-CR
Manufacturer:
ALTERA
Quantity:
1 235
Part Number:
ep7312-CR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
ep7312-CR-90
Manufacturer:
CIRRUSLOG
Quantity:
479
Part Number:
ep7312-CV
Manufacturer:
PANASONIC
Quantity:
35 362
Part Number:
ep7312-CV
Manufacturer:
CIRRUS
Quantity:
591
Part Number:
ep7312-CV
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
ep7312-CV
Quantity:
15
Static Memory Burst Write Cycle
DS508F1
EXPRDY
EXPCLK
WRITE
WORD
WORD
nMWE
nMOE
HALF
nCS
A
D
Note:
1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
4. Address, Data, Halfword, Word, and Write hold state until next cycle.
t
t
HWd
WDd
t
EXs
t
MWd
t
t
t
CSd
Ad
Dv
Figure 10. Static Memory Burst Write Cycle Timing Measurement
t
Dnv
©
t
EXh
Copyright Cirrus Logic, Inc. 2005
t
Ah
t
MWh
(All Rights Reserved)
t
t
MWd
Dv
t
Dnv
t
Ah
t
MWh
High-Performance, Low-Power System on Chip
t
t
MWd
Dv
t
Dnv
t
Ah
t
MWh
t
t
MWd
Dv
t
MWh
EP7312
t
CSh
25

Related parts for ep7312