m30800sagp Renesas Electronics Corporation., m30800sagp Datasheet - Page 52

• Manufacturer Part Number: m30800sagp
• Description: Single-chip 16/32-bit Cmos Microcomputer
• Manufacturer: Renesas Electronics Corporation.

R
R
M
e
E
3
. v
J
Figure 5.6 V
2
0
1
C
3
1 .
B
8 /
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
RD
BCLK
CSi
ADi
BHE
DB
BCLK
CSi
WR,WRL,
WRH
DBi
0
ADi
BHE
0
[Read Timing]
[Write Timing]
0
0
3
N
G
8
o
NOTE:
NOTES:
0 -
o r
. v
3. Varies with operation frequency.
1
u
1. Values guaranteed only when the microcomputer is used independently.
2. Varies with operation frequency.
0
1
p
t
(if external bus cycle is a + b , m=b)
t
t
t
t
(if external bus cycle is a + b , n=(bx2)-1)
, 1
d(DB-WR)
h(WR-DB)
h(WR-AD)
h(WR-CS)
w(WR)
0
CC1
A maximum of 35ns is guaranteed for t
t
t
t
ac1(RD-DB)
ac1(AD-DB)
d(BCLK-AD)
2
0
=(tcyc/2 x n-15)ns.min
0
=V
5
t
t
t
18ns.max
18ns.max
t
=(tcyc x m-20)ns.min
=(tcyc/2-20)ns.min
=(tcyc/2-10)ns.min
=(tcyc/2-10)ns.min
18ns.max
d(BCLK-CS)
18ns.max
d(BCLK-AD)
18ns.max
d(BCLK-CS)
d(BCLK-RD)
CC2
Page 52
(1 + 1 Bus Cycles)
(1 + 1 Bus Cycles)
=(tcyc/2 x m-35)ns.max (if external bus cycle is a + b , m=(b x 2) + 1)
=(tcyc x n-35)ns.max (if external bus cycle is a + b , n = a + b)
tcyc
=3.3V Timing Diagram (1)
tcyc
(1)
(1)
t
d(BCLK-WR)
18ns.max
f o
Hi-Z
5
t
t
ac1(AD-DB)
d(DB-WR)
6
t
ac1(RD-DB)
t
(3)
w(WR)
(2)
t
su(DB-BCLK)
d(BCLK-AD)
30ns.min
(2)
(3)
Measurement Conditions
tcyc=
(1)
t
t
h(WR-DB)
+t
t
t
h(BCLK-WR)
h(WR-CS)
h(WR-AD)
0ns.min
• V
• Input high and low voltage: V
• Output high and low voltage: V
su(DB-BCLK)
CC
f
(BCLK)
1
10
=V
(3)
9
(3)
(3)
CC
t
h(BCLK-AD)
.
2
t
=3.0 to 3.6V
t
h(BCLK-RD)
t
t
h(BCLK-CS)
-3ns.min
h(BCLK-CS)
0ns.min
0ns.min
h(BCLK-AD)
0ns.min
0ns.min
t
t
t
0ns.min
h(RD-AD)
h(RD-DB)
h(RD-CS)
0ns.min
0ns.min
IH
Vcc
=1.5V, V
OH
=1.5V, V
5. Electrical Characteristics
1
=Vcc
IL
=0.5V
OL
2
=1.5V
=3.3V