cop8tab5 National Semiconductor Corporation, cop8tab5 Datasheet - Page 14

• Manufacturer Part Number: cop8tab5
• Description: 8-bit Cmos Rom Microcontroller With 2k Or 4k Memory
• Manufacturer: National Semiconductor Corporation

www.national.com
10.0 Functional Description
There are five CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). With reset the SP is initialized to
RAM address 06F Hex. The SP is decremented as items are
pushed onto the stack. SP points to the next available loca-
tion on the stack.
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
10.3 DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, ACCESS.Bus Interface and the various registers
and counters associated with the timer, T1. Data memory is
addressed directly by the instruction or indirectly by the B, X
and SP pointers.
The data memory consists of 128 bytes of RAM. Sixteen
bytes of RAM are mapped as “registers” at addresses 0F0 to
0FF Hex. These registers can be loaded immediately, and
also decremented and tested with the DRSZ (decrement
register and skip if zero) instruction. The memory pointer
registers X, SP and B are memory mapped into this space at
address locations 0FC to 0FE Hex respectively, with the
other registers being available for general usage.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumu-
lator (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
10.4 OPTION REGISTER
The Option Register, located at address 0x0FFF (hex) in the
ROM Program Memory, is used to configure the user select-
able WATCHDOG, HALT and Oscillator selection options.
The register is defined at the same time as the program
memory as a part of the ROM code and cannot be changed.
The format of the Option register is as follows:
Bit 7
(Continued)
LVCMP
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
Bit 7
COP8TAC5
COP8TAB5
Device
CLKSEL2 RSVD CLKSEL1 CLKSEL0 WATCH
When this bit is set and the ACCESS.Bus is en-
abled, inputs L0, L1 and L2, are compatible with
1.8V logic levels.
Bit 6
Bit 5
Program Memory
Bit 4
Size (ROM)
2048
4096
Bit 3
TABLE 1. Available Memory Address Ranges
DOG
Bit 2
Option Register
Address (Hex)
HALT
0x0FFF (hex)
Bit 1
0x07FF (hex)
FLEX
Bit 0
14
10.2 PROGRAM MEMORY
The program memory consists of 4096 bytes of ROM
Memory. These bytes may hold program instructions or con-
stant data (data tables for the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS
instruction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the device vector to
program memory location 00FF Hex. The program memory
reads 00 Hex in the erased state. Program execution starts
at location 0 after RESET.
If a Return instruction is executed when the SP contains 6F
(hex), instruction execution will continue from Program
Memory location 7FFF (hex). If location 7FFF is accessed by
an instruction fetch, the ROM Memory will return a value of
00. This is the opcode for the INTR instruction and will cause
a Software Trap.
Bit 6
Bit 5
Bits 4, 3 These bits define the two least significant bits of
Bit 2
Bit 1
Bit 0
The COP8 assembler defines a special ROM section type,
CONF, into which the Option Register data may be coded.
The following examples illustrate the declaration of the Op-
tion Register.
Syntax:
[label:].sect
Data Memory
Size (RAM)
= 1
= 0
= 1
= 0
128
This bit defines the most significant bit of the os-
cillaor selection. (See Section 10.6 OSCILLATOR
CIRCUITS ) for more information on Oscillator
selection.)
This bit is provided for program code compatibility
with Flash based devices and can be either one or
zero. The value is ignored in the device. Security
os not required in this device, since the ROM
contained in this device CANNOT be read using
programmers that are capable of reading the com-
patible Flash based device.
the oscillator selection.
WATCHDOG feature disabled. G1 is a general
purpose I/O.
WATCHDOG
WATCHDOG output with weak pullup.
HALT mode disabled.
HALT mode enabled.
This bit is provided for program code compatibility
with Flash based devices and can be either one or
zero. The value is ignored in the device since the
Boot ROM does not exist. Execution following RE-
SET will always be from the Program Memory.
.db
config, conf
value
Segment 0
Segments
Available
feature
enabled.
;1 byte,
Maximum RAM
Address (HEX)
G1
067F
pin
is