cop8tac9 National Semiconductor Corporation, cop8tac9 Datasheet - Page 16

• Manufacturer Part Number: cop8tac9
• Description: 8-bit Cmos Flash Microcontroller With 2k Byte Or 4k Byte Memory
• Manufacturer: National Semiconductor Corporation

www.national.com
10.0 Functional Description
There are five CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). With reset, the SP is initialized to
RAM address 06F Hex. The SP is decremented as items are
pushed onto the stack. SP points to the next available loca-
tion on the stack.
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
10.3 DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, ACCESS.Bus Interface and the various registers
and counters associated with the timer, T1. Data memory is
addressed directly by the instruction or indirectly by the B, X
and SP pointers.
The data memory consists of 128 bytes of RAM. Sixteen
bytes of RAM are mapped as “registers” at addresses 0F0 to
0FF Hex. These registers can be loaded immediately, and
also decremented and tested with the DRSZ (decrement
register and skip if zero) instruction. The memory pointer
registers X, SP and B are memory mapped into this space at
address locations 0FC to 0FE Hex respectively, with the
other registers being available for general usage.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumu-
lator (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
10.4 OPTION REGISTER
The Option register, located at address 0x0FFF (hex) or
0x07FF (hex) in the Flash Program Memory, is used to
configure the user selectable security, WATCHDOG, HALT
and Oscillator selection options. The register can be pro-
grammed only in external Flash Memory programming or
ISP Programming modes. Therefore, the register must be
programmed at the same time as the program memory. The
contents of the Option register shipped from the factory read
00 Hex.
(Continued)
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
COP8TAC9
COP8TAB9
Device
(Flash)(Bytes)
Program
Memory
2048
4096
Size
Flash Memory
TABLE 1. Available Memory Address Ranges
Page Size
(Bytes)
512
Address (Hex)
0x07FF (hex)
0x0FFF (hex)
Register
Option
16
10.2 PROGRAM MEMORY
The program memory consists of 4096 bytes of Flash
Memory. These bytes may hold program instructions or con-
stant data (data tables for the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS
instruction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the device vector to
program memory location 00FF Hex. The program memory
reads 00 Hex in the erased state. Program execution starts
at location 0 after RESET.
If a Return instruction is executed when the SP contains 6F
(hex), instruction execution will continue from Program
Memory location 7FFF (hex). If location 7FFF is accessed by
an instruction fetch, the Flash Memory will return a value of
00. This is the opcode for the INTR instruction and will cause
a Software Trap.
For the purpose of erasing and rewriting the Flash Memory,
it is organized in pages of 512 bytes as shown in Table 1.
The format of the Option register is as follows:
Bit 7
Bit 6
Bit 5
Bits 4, 3 These bits define the two least significant bits of
Bit 2
Bit 1
LVCMP
Bit 7
= 1
= 0
= 1
= 0
= 1
= 0
Data Memory
CLKSEL2
Size (RAM)
When this bit is set and the ACCESS.Bus is en-
abled, inputs L0, L1 and L2, are compatible with
1.8V logic levels.
This bit defines the most significant bit of the os-
cillator selection. (See Section 10.7 OSCILLATOR
CIRCUITS) for more information on Oscillator
selection.)
Security enabled. Flash Memory read and write
are not allowed except in User ISP/Virtual E
mands. Mass Erase is allowed.
Security disabled. Flash Memory read and write
are allowed.
the oscillator selection.
WATCHDOG feature disabled. G1 is a general
purpose I/O.
WATCHDOG
WATCHDOG output with weak pullup.
HALT mode disabled.
HALT mode enabled.
Bit 6
(Bytes)
128
Bit 5
SEC CLKSEL1 CLKSEL0
Bit 4
feature
Segment 0
Segments
Available
RAM
Bit 3
enabled.
WATCH
Bit 2
DOG
Maximum
Address
G1
HALT
Bit 1
(HEX)
RAM
06F
pin
2
FLEX
Bit 0
com-
is