mc56f8335 Freescale Semiconductor, Inc, mc56f8335 Datasheet - Page 12

• Manufacturer Part Number: mc56f8335
• Description: 16-bit Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

1.5 Product Documentation
The documents listed in
56F8335 and 56F8135 devices. Documentation is available from local Freescale distributors, Freescale
semiconductor
http://www.freescale.com.
12
1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0.
pdb_m[15:0]
cdbw[15:0]
pab[20:0]
cdbr_m[31:0]
cdbw[31:0]
xab1[23:0]
xdb2_m[15:0]
xab2[23:0]
IPBus [15:0]
DSP56800E
Reference Manual
56F8300 Peripheral User
Manual
56F8300 SCI/CAN
Bootloader User Manual
56F8335/56F8135
Technical Data Sheet
Errata
Name
Topic
Program data bus for instruction word fetches or read operations.
Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are
used for writes to program memory.)
Program memory address bus. Data is returned on pdb_m bus.
Primary core data bus for memory reads. Addressed via xab1 bus.
Primary core data bus for memory writes. Addressed via xab1 bus.
Primary data address bus. Capable of addressing bytes
cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
Secondary data bus used for secondary data address bus xab2 in the dual memory reads.
Secondary data address bus used for the second of two simultaneous accesses. Capable of addressing
only words. Data is returned on xdb2_m.
Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate as
the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.
sales
Table 1-3
offices,
Detailed description of the 56800E family architecture,
16-bit hybrid controller core processor, and the
instruction set
Detailed description of peripherals of the 56F8300
family of devices
Detailed description of the SCI/CAN Bootloaders
56F8300 family of devices
Electrical and timing specifications, pin descriptions,
device specific peripheral information and package
descriptions (this document)
Details any chip issues that might be present
Table 1-3 Chip Documentation
Table 1-2 Bus Signal Names
are required for a complete description and proper design with the
Freescale
56F8335 Technical Data, Rev. 5
Primary Data Memory Interface Bus
Secondary Data Memory Interface
Description
Program Memory Interface
Peripheral Interface Bus
Literature
Function
Distribution
1
, words, and long data types. Data is written on
DSP56800ERM
MC56F8300UM
MC56F83xxBLUM
MC56F8335
MC56F8335E
MC56F8135E
Centers,
Order Number
Freescale Semiconductor
or
online
Preliminary
at