mc9s08qe16c Freescale Semiconductor, Inc, mc9s08qe16c Datasheet

mc9s08qe16c

Manufacturer Part Number

mc9s08qe16c

Description

8-bit Hcs08 Central Processor Uni

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.MC9S08QE16C.pdf (46 pages)

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Features

• 8-Bit HCS08 Central Processor Unit (CPU)

• On-Chip Memory

• Power-Saving Modes

• Clock Source Options

• System Protection

• Development Support

– Up to 50.33 MHz HCS08 CPU at 3.6 V to 2.4 V, 40 MHz CPU at

– HC08 instruction set with added BGND instruction

– Support for up to 32 interrupt/reset sources

– Flash read/program/erase over full operating voltage and

– Random-access memory (RAM)

– Security circuitry to prevent unauthorized access to RAM and

– Two very low power stop modes

– Reduced power wait mode

– Peripheral clock enable register can disable clocks to unused

– Very low power external oscillator that can be used in run, wait,

– 6 μs typical wakeup time from stop3 mode

– Oscillator (XOSCVLP) — Loop-control Pierce oscillator; crystal

– Internal clock source (ICS) — Internal clock source module

– Watchdog computer operating properly (COP) reset with option to

– Low-voltage warning with interrupt.

– Low-voltage detection with reset or interrupt

– Selectable trip points.

– Illegal opcode detection with reset

– Illegal address detection with reset

– Flash block protection

– Single-wire background debug interface

Freescale Semiconductor

Data Sheet: Technical Data

MC9S08QE32 Series

Covers: MC9S08QE32 and

MC9S08QE16

This document contains information on a product under development. Freescale reserves the

right to change or discontinue this product without notice.

2.4 V to 2.1 V and 20 MHz CPU at 2.1 V to 1.8 V across

temperature range of –40°C to 85°C

temperature

flash contents

modules, thereby reducing currents; allows clocks to remain

enabled to specific peripherals in stop3 mode.

and stop modes to provide accurate clock source to real time

counter.

or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to

16 MHz

containing a frequency-locked-loop (FLL) controlled by internal

or external reference; precision trimming of internal reference

allows 0.2% resolution and 2% deviation over temperature and

voltage; supports CPU frequencies from

4 kHz to 50.33 MHz.

run from dedicated 1 kHz internal clock source or bus clock.

• Peripherals

• Input/Output

• Package Options

– Breakpoint capability to allow single breakpoint setting during

– On-chip in-circuit emulator (ICE) debug module containing

– ADC — 10-channel, 12-bit resolution; 2.5 μs conversion time;

– ACMPx — Two analog comparators with selectable interrupt on

– SCIx — Two serial communications interface modules with

– SPI— One serial peripheral interface; full-duplex or single-wire

– IIC — One IIC; up to 100 kbps with maximum bus loading;

– TPMx — One 6-channel (TPM3) and two 3-channel (TPM1 and

– RTC — (Real-time counter) 8-bit modulus counter with binary

– 40 GPIOs, including 1 output-only pin and 1 input-only pin

– 16 KBI interrupts with selectable polarity

– Hysteresis and configurable pull up device on all input pins;

– 48-pin QFN, 44-pin LQFP, 32-pin LQFP, 28-pin SOIC

in-circuit debugging (plus three breakpoints in on-chip debug

module)

three comparators and nine trigger modes. Eight deep FIFO for

storing change-of-flow addresses and event-only data. Debug

module supports both tag and force breakpoints

automatic compare function; 1.7 mV/°C temperature sensor;

internal bandgap reference channel; operation in stop3; fully

functional from 3.6 V to 1.8 V

rising, falling, or either edge of comparator output; compare

option to fixed internal bandgap reference voltage; outputs can

be optionally routed to TPM module; operation in stop3

optional 13-bit break. Full duplex non-return to zero (NRZ); LIN

master extended break generation; LIN slave extended break

detection; wake on active edge.

bidirectional; double-buffered transmit and receive; master or

slave mode; MSB-first or LSB-first shifting

multi-master operation; programmable slave address; interrupt

driven byte-by-byte data transfer; supports broadcast mode and

10-bit addressing

TPM2); selectable input capture, output compare, or buffered

edge- or center-aligned PWM on each channel;

or decimal based prescaler; external clock source for precise

time base, time-of-day, calendar or task scheduling functions;

free running on-chip low power oscillator (1 kHz) for cyclic

wake-up without external components; runs in all MCU modes

Configurable slew rate and drive strength on all output pins.

MC9S08QE32

48-QFN

Case 1314

7 mm

32-LQFP

Case 873A

7 mm

Document Number: MC9S08QE32

Rev. 3, 11/2008

44-LQFP

Case 824D

28-SOIC

Case 751F

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