mc9s08sf4 Freescale Semiconductor, Inc, mc9s08sf4 Datasheet - Page 7
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mc9s08sf4
Manufacturer Part Number
mc9s08sf4
Description
Mc9s08sf4 Series Freescale Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S08SF4.pdf
(32 pages)
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T
θ
P
P
P
For most applications, P
(if P
Solving
where K is a constant pertaining to the particular part. K can be determined from
P
solving
3.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
During the device qualification ESD stresses were performed for the human body model (HBM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Freescale Semiconductor
JA
A
D
int
I/O
D
= Ambient temperature, °C
= P
(at equilibrium) for a known T
= Package thermal resistance, junction-to-ambient, °C/W
= I
I/O
= Power dissipation on input and output pins — user determined
int
DD
is neglected) is:
Equation 1
Equation 1
+ P
ESD Protection and Latch-Up Immunity
× V
I/O
DD
, Watts — chip internal power
and
and
Equation 2
I/O
Equation 2
<< P
int
K = P
MC9S08SF4 Series MCU Data Sheet, Rev. 2
A
and can be neglected. An approximate relationship between P
iteratively for any value of T
. Using this value of K, the values of P
for K gives:
D
P
× (T
D
= K ÷ (T
A
+ 273°C) + θ
J
+ 273°C)
JA
× (P
D
A
)
.
2
ESD Protection and Latch-Up Immunity
D
and T
Equation 3
J
can be obtained by
by measuring
D
and T
Eqn. 2
Eqn. 3
J
7