mc9s08dn60 Freescale Semiconductor, Inc, mc9s08dn60 Datasheet - Page 217

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mc9s08dn60

Manufacturer Part Number
mc9s08dn60
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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12.1.3
As shown in
prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate
select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256
to get the internal SPI master mode bit-rate clock.
Freescale Semiconductor
BUS RATE
CLOCK
SPI SYSTEM
ENABLE
LSBFE
MSTR
SPE
SPI Baud Rate Generation
CLOCK GENERATOR
Figure
SPIBR
MASTER/SLAVE
MODE SELECT
12-4, the clock source for the SPI baud rate generator is the bus clock. The three
SHIFT
OUT
SHIFT
DIRECTION
Tx BUFFER (WRITE SPID)
Rx BUFFER (READ SPID)
MODE FAULT
DETECTION
SPI SHIFT REGISTER
CLOCK
CLOCK
LOGIC
Figure 12-3. SPI Module Block Diagram
SHIFT
MODF
MC9S08DN60 Series Data Sheet, Rev 2
Rx BUFFER
SPRF
FULL
Tx BUFFER
EMPTY
SHIFT
SPTEF
SPTIE
SPIE
IN
MASTER CLOCK
SLAVE CLOCK
BIDIROE
MODFEN
SPC0
SSOE
Chapter 12 Serial Peripheral Interface (S08SPIV3)
PIN CONTROL
M
S
M
S
M
S
MASTER/
SLAVE
SPI
INTERRUPT
REQUEST
MOSI
(MOMI)
MISO
(SISO)
SPSCK
SS
217

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