c8051t602 Silicon Laboratories, c8051t602 Datasheet - Page 109
c8051t602
Manufacturer Part Number
c8051t602
Description
Mixed Signal Otp Eprom Mcu Family
Manufacturer
Silicon Laboratories
Datasheet
1.C8051T602.pdf
(168 pages)
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Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in
“14.4.2. SMB0CN Control Register” on page 113
ence.
SMBus configuration options include:
•
•
•
•
These options are selected in the SMB0CF register, as described in
tion Register” on page 110
Timeout detection (SCL Low Timeout and/or Bus Free Timeout)
SDA setup and hold time extensions
Slave event enable/disable
Clock source selection
.
Rev. 0.5
; Table 14.4 provides a quick SMB0CN decoding refer-
C8051T600/1/2/3/4/5
Section “14.4.1. SMBus Configura-
Section
109
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