c8051f544 Silicon Laboratories, c8051f544 Datasheet - Page 154

• Manufacturer Part Number: c8051f544
• Description: Mixed Signal Isp Flash Mcu Family
• Manufacturer: Silicon Laboratories

C8051F54x
SFR Definition 18.1. XBR0: Port I/O Crossbar Register 0
SFR Address = 0xE1; SFR Page = 0x0F
154
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
Reserved Always Write to 0.
SMB0E
CP1AE
CP0AE
URT0E
SPI0E
Name
CP1E
CP0E
CP1AE
R/W
7
0
Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1 unavailable at Port pin.
1: Asynchronous CP1 routed to Port pin.
Comparator1 Output Enable.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SMBus I/O Enable.
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
CP1E
R/W
6
0
CP0AE
R/W
5
0
CP0E
R/W
Rev. 1.0
4
0
Function
SMB0E
R/W
3
0
SPI0E
R/W
2
0
Reserved
R
1
0
URT0E
R/W
0
0