z8f1601 ZiLOG Semiconductor, z8f1601 Datasheet - Page 180

• Manufacturer Part Number: z8f1601
• Description: Z8 Encore!? Microcontroller With Flash Memory And 10-bit A/d Converter
• Manufacturer: ZiLOG Semiconductor

Table 95. OCD Status Register (OCDSTAT)
PS017609-0803
RESET
FIELD
BITS
R/W
OCD Status Register
DBG
BRKEN—Breakpoint Enable
This bit controls the behavior of the BRK instruction (opcode 00H). By default, Break-
points are disabled and the BRK instruction behaves like a NOP. If this bit is set to 1, when
a BRK instruction is decoded, the DBGMODE bit of the OCDCTL register is automatically
set to one.
0 = Breakpoints are disabled.
1 = Breakpoints are enabled.
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends
an Debug Acknowledge character (
occurs.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
Reserved
These bits are reserved and must be 0.
RST—Reset
Setting this bit to 1 resets the Z8F640x family device. The device goes through a normal
Power-On Reset sequence with the exception that the On-Chip Debugger is not reset. This
bit is automatically cleared to 0 when the reset finishes.
0 = No effect.
1 = Reset Z8F640x family device.
The OCD Status register reports status information about the current state of the debugger
and the Z8F640x family device.
DBG—Debug Status
0 = The Z8F640x family device is operating in normal mode.
1 = The Z8F640x family device is in Debug mode.
HALT—Halt Mode
0 = The Z8F640x family device is not in Halt mode.
1 = The Z8F640x family device is in Halt mode.
R
7
0
HALT
R
6
0
RPEN
R
5
0
FFH
R
4
0
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
) to the host when a Breakpoint or Watchpoint
R
3
0
Reserved
R
2
0
On-Chip Debugger
R
1
0
Z8 Encore!
R
0
0
®
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