ep9312 Cirrus Logic, Inc., ep9312 Datasheet - Page 14

• Manufacturer Part Number: ep9312
• Description: Universal Platform System-on-chip Processor
• Manufacturer: Cirrus Logic, Inc.

EP9312
Universal Platform SOC Processor
Timings
Timing Diagram Conventions
This data sheet contains one or more timing diagrams. The following key explains the components used in these
diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached
unless specifically stated.
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements.
14
• T
• CVDD = VDD_PLL = 1.8V
• RVDD = 3.3 V
• All grounds = 0 V
• Logic 0 = 0 V, Logic 1 = 3.3 V
• Output loading = 50 pF
• Timing reference levels = 1.5 V
• The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between
33 MHz and 100 MHz (92 MHz for industrial conditions).
A
= 0 to 70° C
©
Copyright 2005 Cirrus Logic (All Rights Reserved)
Bus/Signal Omission
Valid Bus to Tristate
Figure 1. Timing Diagram Drawing Key
Undefined/Invalid
High/Low to High
Bus Change
High to Low
Bus Valid
Clock
DS515PP7