attiny11 ATMEL Corporation, attiny11 Datasheet - Page 46

• Manufacturer Part Number: attiny11
• Description: 8-bit Microcontroller With 1k Byte Flash
• Manufacturer: ATMEL Corporation

46
ATtiny11/12
• Bit 4 - ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined
by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit
is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut-
ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a
logic one to the flag.
• Bit 3 - ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Ana-
log Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled.
• Bit 2 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny11/12 and will always read as zero.
• Bits 1,0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator Inter-
rupt. The different settings are shown in Table 20.
Table 20. ACIS1/ACIS0 Settings
Note:
Caution: Using the SBI or CBI instruction on bits other than ACI in this register will write
a one back into ACI if it is read as set, thus clearing the flag.
ACIS1
0
0
1
1
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-
abled by clearing its interrupt enable bit in the ACSR register. Otherwise, an interrupt can
occur when the bits are changed.
ACIS0
0
1
0
1
Comparator Interrupt on Output Toggle
Reserved
Comparator Interrupt on Falling Output Edge
Comparator Interrupt on Rising Output Edge
Interrupt Mode
1006F–AVR–06/07