s1s65000 Epson Electronics America, Inc., s1s65000 Datasheet - Page 4

• Manufacturer Part Number: s1s65000
• Description: Network Camera Controller With Jpeg Encoder
• Manufacturer: Epson Electronics America, Inc.

S1S65000
! ! ! ! PIN DESCRIPTION
Cell Type Description
Pin Description
4
ICS
ICD1
ICU1
ICSU1
BLNC4
BLNC4U1
BLNC4D2
BLNS4
BLNS4D1
OLN4
OTLN4
OLTR
(MA [21:20])
MA [19:12]
MA 11
MA [10:0]
MD [15:0]
MCS [2:0]#
MOE#
#:
I:
O:
IO:
P:
Cell Type
Pin Name
# at the right end of a pin name indicates a low active signal.
Input pin
Output pin
Bi-directional pin
Power Supply
LVCMOS Schmitt input
LVCMOS input with pull down resistor (50k @3.3V)
LVCMOS input with pull up resistor (50k @3.3V)
LVCMOS Schmitt input with pull up resistor
Low noise LVCMOS IO buffer ( 4mA)
Low noise LVCMOS IO buffer with pull-up resistor (50k @3.3V) ( 4mA)
Low noise LVCMOS IO buffer with pull-down resistor (100k @3.3V) ( 4mA)
Low noise LVCMOS Schmitt IO buffer ( 4mA)
Low noise LVCMOS Schmitt IO buffer with pull-down resistor (50k @3.0V)
( 4mA)
Low noise output buffer ( 4mA)
Low noise Tri-state output buffer ( 4mA)
Low Voltage Transparent Output
Type
(I/O)
I/O
O
O
O
O
O
BLNC4D2
(BLNS4)
OLN4
OLN4
OLN4
OLN4
OLN4
Type
Cell
21-24, 27-30,
32-35, 37-40
(114-115)
128-131,
134-138,
143-144
140-141
Pin No.
Description
7, 1-5,
8-10
142
12
EPSON
See GPIOD [1:0] for more detail of these pins.
Address outputs [19:12]
This pin has the following functions:
" MA11: Address output 11 (Default pin function)
" CFREG# output
These pins have the following functions:
" MA [10:0]: Address outputs [10:0] (Default pin function)
" CFADDR [10:0] outputs
These pins have the following functions:
" 16-bit Data bus for memory (Default pin function)
" Data Bus for CF Card.
" MODESEL [15:0]
Chip select signals for memory (SDRAM and static memories) (Low active)
This pin has the following functions (Low active)
" MOE#: Read strobe signal for memory read cycle. (Default pin function)
" CFOE#: Enable signal for CF read cycle
During the CompactFlash (CF) cycles, this signal behaves as the
REG# signal selecting attribute or I/O space of the CF card.
During the CF cycles, these signals become the CF interface address
signal [10:0].
At the power ON reset time (RESET# is changed from LOW to HIGH),
these pins are sampled to determine the internal operation mode. See
“SYSTEM CONFIGURATION by MODESEL PIN” for more details.
To determine the operation mode, a pull-up resistance may be required
externally. (Resistor value: 4.7k
During the CF cycle, this signal becomes output enable signal for CF
common memory or attribute space access.
Out of these, MA [15:14] become BA [1:0] as a bank address, when
using SDRAM
Use MCS2# to support an SDRAM
Description
TCK, CLKI, RESET#
TESTEN
TMS, TDI
TRST#
MII
CF Interface
MD [15:0]
GPIOA, GPIOB, GPIOD [1:0]
Camera Interface
MEMC Interface (excluding MD)
TDO
VCP
to 10k
Applicable pin example
range)