a8450 Allegro MicroSystems, Inc., a8450 Datasheet - Page 9

• Manufacturer Part Number: a8450
• Description: Automotive Multioutput Voltage Regulator
• Manufacturer: Allegro MicroSystems, Inc.

ENBAT is an edge-triggered enable (logic 1 ≥ 2.7 V), which
is used to enable the A8450 in response to a high-voltage
signal, such as from an automobile ignition or battery switch.
In this capacity, ENBAT is used only as a momentary switch
to wake up the device. If there is no need for a high-voltage
signal, ENBAT can be pulled low continuously.
ENB is used to initiate the reset of the device. If ENBAT is
pulled low, ENB acts as a single reset control.
Diagnostics. An open drain output, through the NFAULT
pin, is pulled low to signal to a DSP or microcontroller any of
the following fault conditions:
• V5A, the 5 V analog regulator output, is shorted to supply
• Either or both of the V5A and the V5D regulator outputs
• Device junction temperature, T
Charge Pump. The charge pump generates a voltage above
V
buck switch. A 0.1 μF ceramic monolithic capacitor, C7, should
be connected between the VCP pin and the VBB pin, to act as
a reservoir to run the buck converter switching regulator.
V
disabled in the case of a fault condition. In addition, a 0.1 μF
ceramic monolithic capacitor, C8, should be connected between
CP1 and CP2.
Power On Reset Delay. The POR block monitors the sup-
ply voltages and provides a signal that can be used to reset a
DSP or microcontroller. A POR event is triggered by any of
the following conditions:
• Either V33 or VADJ is pulled below its UVLO threshold,
A8450KLB-DS, Rev. 2
BB
CP
are below their UVLO threshold, V
Warning threshold, T
V
UVLOV33
is internally monitored to ensure that the charge pump is
in order to provide adequate gate drive for the N-channel
or
V
UVLOVADJ
JTW
. This occurs if the current limit
J
, exceeds the Thermal
UVLOV5
Automotive Multioutput Voltage Regulator
• Both input signal pins, ENB and ENBAT, are pulled low.
• V
• During any normal power-on, V
An open drain output, through the NPOR pin, is provided to
signal a POR event to the DSP or microcontroller. The reset
occurs after an adjustable delay, t
tor, C9, connected to the CPOR pin. The value of t
calculated using the following formula
where C
A POR can be forced without a significant drop in the supply
voltage, V
pins. However, pulse duration should be short enough so that
V
Thermal Shutdown. When the device junction temperature,
T
warning temperature, T
pin. At the same time, a thermal shutdown circuit disables the
buck converter, protecting the A8450 from damage.
J
REG
on either regulator,
the VREG voltage falls below V
exceeding I
This immediately pulls the NPOR pin low, indicating that
the device is beginning a power-off sequence. In addition,
the buck converter switching regulator is disabled, and
the VREG supply begins to ramp down. The rate at which
V
and value of the output capacitors (C1, C2, C3, and C4).
V
, is sensed to be at T
REG
UVLOVADJ
REG
does not drop significantly.
drops below its UVLO threshold,
decays is dependent on the total current draw, I
CPOR
REG
, triggering a POR.
DSLIM
(μF) is the value of the C9 capacitor.
, by pulsing low both the ENB and the ENBAT
.
t
POR
V
JTW
OC
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
JTSD
= 2.13
, is exceeded. It also occurs if
), a fault is indicated at the NFAULT
(≈15°C higher than the thermal
×
POR
10
OUTVADJ
REGMON
5
, set by an external capaci-
×
C
CPOR
V
, due to current
falls below
UVLOVREG
A8450
POR
.
(ms) is
LOAD
9
,