bd8372hfp-m ROHM Co. Ltd., bd8372hfp-m Datasheet - Page 15

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bd8372hfp-m

Manufacturer Part Number
bd8372hfp-m
Description
Led Drivers For Automotive Light
Manufacturer
ROHM Co. Ltd.
Datasheet
●Notes for use
BD8372HFP-M,BD8372EFJ-M
© 2011 ROHM Co., Ltd. All rights reserved.
www.rohm.com
10. Input terminal
11. About a steep change of the Vcc voltage
1. Absolute maximum ratings
2. Reverse polarity connection
3. Power supply line
4. GND line
5. Thermal design
6. Short circuit mode between terminals and wrong mounting
7. Radiation
8. TSD (Thermal Shut-Down)
9. Inspection by the set circuit board
We are careful enough for quality control about this IC. So, there is no problem under normal operation, excluding that it
exceeds the absolute maximum ratings. However, this IC might be destroyed when the absolute maximum ratings, such
as impressed voltages or the operating temperature range (Topr), is exceeded, and whether the destruction is short circuit
mode or open circuit mode cannot be specified. Please take into consideration the physical countermeasures for safety,
such as fusing, if a particular mode that exceeds the absolute maximum rating is assumed.
Connecting the power line to the IC in reverse polarity (from that recommended) will damage the part. Please utilize the
direction protection device as a diode in the supply line.
Please design the power supply line where a large current is thrown to reduce the resistance of the wiring for the power
supply pattern so that there is a possibility of usually influencing operation.
The ground line is where the lowest potential and transient voltages are connected to the IC.
Please confirm whether there is actually terminal that is the voltage of GND or less including transients.
Do not exceed the power dissipation (Pd) of the package specification rating under actual operation, and please design
enough temperature margins. This product has exposed the frame to the back side of the package, but please note that it
is assumed to use heat radiation efficiency by the heat radiation for this part. Please take the heat radiation pattern on not
only the surface of the substrate but also the back of the substrate widely.
Do not mount the IC in the wrong direction and displacement, and be careful about the reverse-connection of the power
connector. Moreover, this IC might be destroyed when the dust short the terminals between them or GND.
( The outputs of CH1(pin2,3) have NO protection circuit. So please especially be careful about them.)
Strong electromagnetic radiation can cause operation failures.
The TSD is activated when the junction temperature (Tj) exceeds Tjmax, and the output terminal is switched to OPEN.
The guarantee and protection of set are not purpose. Therefore, please do not use this IC after TSD circuit operates, nor
use it for assumption that operates the TSD circuit.
The stress might hang to IC by connecting the capacitor to the terminal with low impedance. Then, please discharge
electricity in each and all process. Moreover, when attaching or detaching from jig in the inspection process, please turn off
the power before mounting the IC, and turn on after mounting the IC, and vice versa. In addition, please take into
consideration the countermeasures for electrostatic damage, such as giving the earth in assembly process, transportation
or preservation.
This IC is a monolithic IC, and has P
junction is firmed in this P-layer and N-layer of each element. For instance, the resistor or the transistor is connected to the
terminal as shown in the figure below. When the GND voltage potential is greater than the voltage potential at Terminals A
on the resistor, at Terminal B on the transistor, the PN junction operates as a parasitic diode. In addition, the parasitic NPN
transistor is formed in said parasitic diode and the N layer of surrounding elements close to said parasitic diode. These
parasitic elements are formed in the IC because of the voltage relation. The parasitic element operating causes the
interference of circuit operation, then the wrong operation and destruction. Therefore, please be careful so as not to
operate the parasitic elements by impressing to input terminals lower voltage than GND (P substrate). Please do not apply
the voltage to the input terminal when the power-supply voltage is not impressed. Moreover, please impress each input
terminal lower than the power-supply voltage or equal to the specified range in the guaranteed voltage when the
power-supply voltage is impressing.
There is a possibility of generating a large current because MOS is used for the output transistor when the input voltage
change is steep. Please select external parts after it verifies it enough by a real application including the transition change.
Terminal-A
Parasitic
element
P
+
+
isolation and P substrate for the element separation. Therefore, a parasitic PN
GND
Example of IC of simple structure
P
Resistor
P-Substrate
P
+
Terminal-A
15/16
Parasitic
element
Terminal-B
Parasitic
element
P
+
C
B
Transistor(NPN)
E
GND
P-Substrate
P
P
+
GND
Terminal-B
Surrounding
elements
B
C
E
GND
Parasitic
element
Technical Note
2011.04 - Rev.A

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