lt3804 Linear Technology Corporation, lt3804 Datasheet - Page 8

• Manufacturer Part Number: lt3804
• Description: Secondary Side Dual Output Controller With Opto Driver
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
LT3804
Synchronization and Oscillator Frequency Setting
The switching is synchronized to the secondary winding
falling edge and the synchronization threshold is typically
2.5V. The synchronization falling edge triggers an internal
inverted ramp (see Figure 2) and starts a new switching
cycle for the leading edge voltage mode PWM. The reason
for using leading edge modulation is to leave the trans-
former primary side peak current sensing undisturbed.
For proper synchronization, the oscillator frequency should
be set lower than the system switching frequency with
tolerances taken into account.
f
0.8 is the tolerance of f
For example, given a system operating at 200kHz with
15% tolerance, then f
f
Once f
For f
Output Voltage Programming
The LT3804 uses true remote sensing (separate ground
sensing pins, GNDS1 for the first output and GNDS2 for
the second output) to eliminate output error pickup due to
parasitic resistance.
The feedback reference voltages V
referred to GNDS1 and GNDS2 respectively. The output
voltage can be easily programmed by a resistor divider, as
shown in the Block Diagram:
where R14 connects to GNDS1 and R4 connects to
GNDS2.
8
SL
OSC
f
CSET = (103540pF/f
V
V
OSC
is the low limit of the system switching frequency and
OUT1
OUT2
OSC
< (170kHz • 0.8), so f
OSC
< (f
= 200kHz, CSET = 500pF.
= 0.6 (1 + R13/R14)
= 0.6 (1 + R3/R4)
is determined, CSET can be calculated by
SL
• 0.8)
U
SL
OSC(kHz)
OSC
= 200kHz • 85% = 170kHz; and
OSC
U
.
should be set below 136kHz.
) – 18pF.
REF1
W
and V
REF2
U
are 0.6V
For accurate sensing results, GNDS1 and GNDS2 should
stay within –0.1V and 0.1V referred to GND. Note that if
either GNDS1 or GNDS2 is not connected, the LT3804 will
be shut down.
Power Good
When both outputs reach between 90% and 110% of the
programmed level, V
required if the function is used) to signal power good. If
either output rises above 110% or drops below 90%,
V
first output and PGIN2 senses the second output with a
resistor divider. PGIN1 and PGIN2 are compared to the
references V
should be connected to GNDS1 and GNDS2 with respect
to each output.
Current Limit CA1
The first output current limit is set by the 50mV threshold
across CL1P and CL1N, the inputs of the amplifier CA1. By
connecting an external resistor R
the current limit is set for 50mV/R
stablizes the current limit loop. If current limit is not used,
both CL1P and CL1N should be grounded and C17 is not
needed.
Current Limit CA2
The second output current limit is set by the 50mV
threshold across CL2P and CL2N, the inputs of the ampli-
fier CA2. By connecting an external resistor R
Diagram), the current limit is set for 50mV/R
on I
is not used, both CL2P and CL2N should be grounded and
the BGS pin should also be grounded to disable compara-
tor CA2; R6 and C6 are not needed.
PGOOD
LCOMP2
goes low after a 200 s delay. PGIN1 senses the
stablize the current limit loop. If current limit
REF1
and V
PGOOD
REF2
goes high( a pull-up resistor is
respectively. Resistor dividers
S1
(see Block Diagram),
S1
. C17 on I
S2
S2
. R6 and C6
(see Block
LCOMP1
3804i