MC100LVEL31DG ON Semiconductor, MC100LVEL31DG Datasheet - Page 2

• Manufacturer Part Number: MC100LVEL31DG
• Description: IC FLIP FLOP ECL 3.3V S/R 8SOIC
• Manufacturer: ON Semiconductor
• Series: 100LVELr
• Type: D-Typer

Specifications of MC100LVEL31DG

• Function: Set(Preset) and Reset
• Output Type: Differential
• Number Of Elements: 1
• Number Of Bits Per Element: 1
• Frequency - Clock: 2.9GHz
• Delay Time - Propagation: 475ps
• Trigger Type: Positive Edge
• Voltage - Supply: 3 V ~ 3.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Number Of Circuits: 1
• Logic Family: 100
• Logic Type: D-Type Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 0.59 ns
• Supply Voltage (max): - 3.8 V, 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): - 3 V or 3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: MC100LVEL31DGOS

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 3. MAXIMUM RATINGS
V
V
V
I
T
T
q
q
q
q
q
T
q
Symbol
out
A
stg
JA
JC
JA
JC
JA
sol
JC
Table 1. PIN DESCRIPTION
CC
EE
I
PIN
CLK
Q, Q
D
R
S
V
V
EP
CC
EE
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Wave Solder
Thermal Resistance (Junction−to−Case)
(DFN8 only) Thermal exposed pad must be connected to a
sufficient thermal conduit. Electrically connect to the most
negative supply (GND) or leave unconnected, floating open.
FUNCTION
ECL Clock Input
ECL Differential Data Outputs
ECL Data Input
ECL Reset Input
ECL Set Input
Positive Supply
Negative Supply
Parameter
Figure 1. Logic Diagram and Pinout Assignment
CLK
S
R
D
Pb−Free
1
2
3
4
Pb
http://onsemi.com
V
V
V
V
Continuous
Surge
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
(Note 1)
D
EE
CC
EE
CC
Flip Flop
Condition 1
= 0 V
= 0 V
= 0 V
= 0 V
S
R
2
V
V
8 SOIC
8 SOIC
8 SOIC
8 TSSOP
8 TSSOP
8 TSSOP
DFN8
DFN8
DFN8
8
7
6
5
I
I
≤ V
≥ V
Condition 2
CC
EE
V
Q
Q
V
CC
EE
Table 2. TRUTH TABLE
Z = LOW to HIGH Transition
X = Don’t Care
D
H
X
X
X
L
S
H
H
L
L
L
R
H
H
L
L
L
41 to 44 ± 5%
41 to 44 ± 5%
−65 to +150
−40 to +85
35 to 40
Rating
−6 to 0
−8 to 0
CLK
8 to 0
6 to 0
100
190
130
185
140
129
265
265
Z
Z
X
X
X
50
84
Undef
Q
H
H
L
L
Undef
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Unit
mA
mA
°C
°C
°C
Q
H
H
V
V
V
V
L
L