MC100EL51DG ON Semiconductor, MC100EL51DG Datasheet - Page 2

• Manufacturer Part Number: MC100EL51DG
• Description: IC FLIP FLOP ECL DIFF CLK 8SOIC
• Manufacturer: ON Semiconductor
• Series: 100ELr
• Type: D-Typer

Specifications of MC100EL51DG

• Function: Reset
• Output Type: Differential
• Number Of Elements: 1
• Number Of Bits Per Element: 1
• Frequency - Clock: 2.8GHz
• Delay Time - Propagation: 475ps
• Trigger Type: Positive Edge
• Voltage - Supply: 4.2 V ~ 5.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Other names: MC100EL51DGOS

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 3. MAXIMUM RATINGS
V
V
V
I
T
T
q
q
q
q
q
T
q
Symbol
out
A
stg
JA
JC
JA
JC
JA
sol
JC
Figure 1. Logic Diagram and Pinout Assignment
CC
EE
I
CLK
CLK
D
R
1
2
3
4
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Wave Solder
Thermal Resistance (Junction−to−Case)
D
Parameter
R
8
7
6
5
Pb−Free
V
Q
Q
V
CC
EE
Pb
http://onsemi.com
V
V
V
V
Continuous
Surge
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
(Note 1)
EE
CC
EE
CC
Condition 1
= 0 V
= 0 V
= 0 V
= 0 V
2
Table 2. PIN DESCRIPTION
Table 1. TRUTH TABLE
Z = LOW to HIGH Transition
* Pin will default low when left open.
**Pin will default low when inputs are left open.
R
D
CLK, CLK
Q, Q
V
V
EP
CC
EE
PIN
D*
H
X
L
V
V
8 SOIC
8 SOIC
8 SOIC
8 TSSOP
8 TSSOP
8 TSSOP
DFN8
DFN8
DFN8
I
I
 V
 V
Condition 2
CC
EE
ECL Reset Input
ECL Data Input
ECL Clock Inputs
ECL Data Outputs
Positive Supply
Negative Supply
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND)
or leave unconnected, floating open.
R*
H
L
L
FUNCTION
CLK*
Z
Z
X
41 to 44 ± 5%
−65 to +150
−40 to +85
41 to 44
35 to 40
Rating
100
190
130
185
140
129
265
265
−8
−6
50
84
8
6
Q**
H
L
L
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Unit
mA
mA
°C
°C
°C
V
V
V
V