tc5747 ETC-unknow, tc5747 Datasheet - Page 2

• Manufacturer Part Number: tc5747
• Description: Single Chip Cmos Imager With Integrated Image Signal Processor Jpeg Codec
• Manufacturer: ETC-unknow

1.
2.
3.
4.
1.1
1.2
1.3
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3.1
3.2
3.3
4.1
4.2
4.3
INTRODUCTION .................................................................................................................................................. 1
FUNCTIONAL DESCRIPTION ........................................................................................................................... 5
RESET AND CLOCK .......................................................................................................................................... 11
3.1.1
3.1.2
3.1.3
TC5747MF24L INTERFACES ........................................................................................................................... 13
4.1.1
4.1.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
F
S
C
CONT............................................................................................................................................................... 5
RCLK ............................................................................................................................................................... 5
IMGA............................................................................................................................................................... 6
YUVR .............................................................................................................................................................. 6
JPEG ................................................................................................................................................................ 6
PVI
I
P
B
R
A
O
B
JPEG C
L
PLL C
D
I
P
S
MAGER AND
2
EATURES
PECIFICATIONS
IXEL
ARALLEL
ERIAL
OW
OMPACT
AYER
ESOLUTIONS AND
NALOG
N
AYER TO
C S
EVICE
Startup ....................................................................................................................................................... 11
Bypass........................................................................................................................................................ 11
Power Down .............................................................................................................................................. 11
Overview .................................................................................................................................................... 13
Mode of Operation..................................................................................................................................... 14
Parallel Mode of Operation....................................................................................................................... 17
External Chip-Select .................................................................................................................................. 19
Qualified Clock Mode ................................................................................................................................ 19
VALIDH Configured as WR#..................................................................................................................... 20
Frame-Rate Control................................................................................................................................... 20
Data ........................................................................................................................................................... 21
Data Markers............................................................................................................................................. 23
Ancillary Data Format............................................................................................................................... 25
Serial Output Mode.................................................................................................................................... 26
-
CHIP
AND
ERIAL
P
A
ONFIGURATIONS
OWER
G
V
OMPRESSION
RRAY
I
NITIALIZATION
M
SVI .................................................................................................................................................... 6
RID
P
IDEO
24-
......................................................................................................................................................... 1
ROCESSING
YUV T
V
ICRO
I
NTERFACE
IDEO
M
A
C
PIN
C
I
ONFIGURATION
DDRESS
ODES
NTERFACE
ONFIGURATION
................................................................................................................................................ 3
C
C
I
ONTROLLER
RANSLATION
NTERFACE
AMERA
F
RAME
....................................................................................................................................... 11
U
....................................................................................................................................... 8
NIT
................................................................................................................................... 11
................................................................................................................................... 13
G
S
ENERATOR
EQUENCE
.............................................................................................................................. 28
(JCOR)................................................................................................................... 9
M
R
ATES
ODULE
(PVI) ............................................................................................................... 17
.......................................................................................................................... 7
.......................................................................................................................... 8
........................................................................................................................ 7
U
Table of Contents
NIT
.................................................................................................................... 8
................................................................................................................ 12
................................................................................................................. 7
................................................................................................................ 4
(YUVR)................................................................................................. 9
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