icl8068a Intersil Corporation, icl8068a Datasheet - Page 6

• Manufacturer Part Number: icl8068a
• Description: Precision 4 1/2 Digit, A/d Converter
• Manufacturer: Intersil Corporation

System Electrical Specifications: ICL8052A/ICL71C03
V++ = +15V, V+ = +5V, V- = -15V, T
NOTES:
10. Tested in 3
11. Tested in 4
12. Tested with a low dielectric absorption integrating capacitor. See Component Selection Section.
13. The temperature range can be extended to 70
Detailed Description
Analog Section
Figure 2 shows the equivalent Circuit of the Analog Section
of both the ICL71C03/8052A and the ICL71C03/8068A in
the 3 different phases of operation. IF the RUN/HOLD pin is
left open or tied to V+, the system will perform conversions
at a rate determined by the clock frequency: 40,0002 at 4
digit and 4002 at 3
Figure 3 for details of conversion timing).
Auto-Zero Phase I
During the Auto-Zero, the input of the buffer is connected to
V
the integrator and comparator, the purpose of which is to
charge the auto-zero capacitor until the integrator output
does not change with time. Also, switches 1 and 2 recharge
the reference capacitor to V
Input Integrate Phase II
During Input Integrate the auto-zero loop is opened and the
ANALOG INPUT is connected to the BUFFER INPUT
through switch 4 and C
buffer, integrator and comparator will see the same voltage
that existed in the previous state (Auto-Zero). Thus, the
integrator output will not change but will remain stationary
during the entire Input Integrate cycle. If V
zero, and unbalanced condition exists compared to the Auto
Differential Linearity (Difference between
Worst Case Step of Adjacent Counts and
Ideal Step)
Rollover Error (Difference in Reading for
Equal Positive & Negative Voltage Near
Full Scale)
Noise (Peak-To-Peak Value Not
Exceeded 95% of Time)
Leakage Current at Input
Zero Reading Drift
Scale Factor Temperature Coefficient
REF
temperature leakage of the 8068A.
through switch 2, and switch 3 closes a loop around
PARAMETER
1
1
/
/
2
2
digit (2,000 count) circuit shown in Figure 5, clock frequency 12kHz. Pin 2 71C03 connected to GND.
digit (20,000 count) circuit shown in Figure 5, clock frequency 120kHz. Pin 2 71C03A open.
1
/
2
digit clock periods per cycle (see
(Figure 2A)
REF
. If the input signal is zero, the
REF
(Figure 2B)
6
A
.
= 25
ICL8052A/ICL71C03, ICL8068A/ICL71C03
o
C, f
-2V ≤ V
-V
V
Full Scale = 200mV,
Full Scale = 2V
V
V
0
V
0
Ext. Ref. 0ppm/
o
o
IN
IN
IN
IN
IN
C To 70
C To 70
CLK
IN
= 0V,
= 0V
= 0V,
= 2V,
CONDITIONS
≅ +V
o
is not equal to
Set for 3 Reading/Sec. (Continued)
IN
C and beyond if the Auto-Zero and Reference capacitors are increased to absorb the high
TEST
IN
≤ +2V
o
o
C
C,
≈ 2V
o
C
1
/
2
MIN
-
-
-
-
-
-
ICL8052A/ICL71C03
Zero phase, and the integrator will generate a ramp whose
slope is proportional to V
sign of the ramp is latched into the polarity F/F.
Deintegrate Phase II
During the Deintegrate phase, the switch drive logic uses the
output of the polarity F/F in determining whether to close
switch 6 or 5. If the input signal is positive, switch 6 is closed
and a voltage which is V
Auto-Zero is impressed on the BUFFER INPUT. Negative
Inputs will cause +2(V
INPUT via switch 5. Thus, the reference capacitor generates
the equivalent of a (+) or (-) reference from the single
reference voltage with negligible error. The reference voltage
returns the output of the integrator to the zero-crossing point
established in Phase I. The time, or number of counts,
required to do this is proportional to the input voltage. Since
the Deintegrate phase can be twice as long as the Input
Integrate Phase, the input voltage required to give a full
scale reading is 2V
(NOTE 9)
TYP
0.01
0.2
20
50
5
1
3
MAX
30
15
1
5
-
-
-
REF
MIN
REF
ICL8052A/A/ICL71C03
.
-
-
-
-
-
-
-
REF
(Figures 2C and 2D)
IN
) to be applied to the BUFFER
. At the end of this phase, the
(NOTE 10)
more negative than during
TYP
0.01
0.5
0.5
30
3
2
MAX
10
1
2
5
-
-
-
ppm/
Counts
Counts
UNITS
µV/
µV
pA
o
o
C
C