ncv4299a ON Semiconductor, ncv4299a Datasheet - Page 11

• Manufacturer Part Number: ncv4299a
• Description: Ncv4299a 150 Ma Low-dropout Voltage Regulator
• Manufacturer: ON Semiconductor

Reset Output (RO)
generated as the IC powers up. After the output voltage V
increases above the reset threshold voltage V
timer D is started. When the voltage on the delay timer V
passes V
steady state is typically 2.4 V. A discharge of the delay timer
(V
Reset Adjust (RADJ)
value of 4.64 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figure 18. The resistor divider keeps the voltage
above the V
voltages and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
should be connected to GND causing the reset threshold to
go to its default value (typ. 4.64 V).
A reset signal, Reset Output (RO, low voltage) is
The reset threshold V
If the reset adjust option is not needed, the RADJ−pin
D
V THRES + V RADJ, TH · (R ADJ1 ) R ADJ2 ) R ADJ2
) is started when V
V
RO,SAT
V
UD
V
V
UD
RT
LD
V
V
, the reset signal RO goes high. D pin voltage in
V
RO
Power−on−Reset
V
Q
RADJ,TH
D
I
t
d
, (typ. 1.36 V), for the desired input
RT
Q
drops and stays below the reset
can be decreased from a typical
Shutdown
Thermal
t
RR
Figure 19. Reset Timing Diagram
RT
, the delay
Voltage Dip
at Input
http://onsemi.com
(eq. 1)
Q
D
11
Undervoltage
threshold voltage V
(V
output voltage V
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
guaranteeing that RO is valid for V
Reset Delay (D)
capacitor C
provides charge current I
delay capacitor C
The reset output RO is an open collector NPN transistor,
The reset delay circuit provides a delay (programmable by
D
) drops below the lower threshold voltage V
1. During Powerup (once the regulation threshold has
2. After a reset event has occurred and the device
been exceeded).
is back in regulation. The delay capacitor is
set to discharge when the regulation (V
threshold voltage) has been violated. When
the delay capacitor discharges to down to V
the reset signal RO pulls low.
D
) on the reset output RO lead. The delay lead D
Secondary
RO
D
Spike
RT
during the following times:
is brought low to reset the processor.
. When the voltage of the delay timer
D
< t
(typically 7.1 mA) to the external
RR
Overload
at Output
dV
dt
Q
+
as low as 1.0 V.
C D
I D
LD
RT
, reset
, the reset
t
t
t
t
LD
,