W83977EF Winbond Electronics Corp America, W83977EF Datasheet - Page 57

• Manufacturer Part Number: W83977EF
• Description: Description = W83877TF Plus Kbc, GP I/O, Wake-Up, Power Fail Resume ;; Package = QFP 128
• Manufacturer: Winbond Electronics Corp America

Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
TABLE 3-4 INTERRUPT CONTROL FUNCTION
Bit
3
0
0
0
1
3.2.6 Interrupt Status Register (ISR) (Read only)
a logical 0 by itself after being set to a logical 1.
other bits of UFR are programmed.
out interrupt is pending.
this bit will be set to a logical 0.
Bit
2
0
1
1
1
ISR
Bit
1
0
1
0
0
Bit
0
1
0
0
0
Interrupt
priority
First
Second
Second
7
-
6
Interrupt Type
UART Receive
Status
RBR Data Ready
FIFO Data Timeout
0
5
4
0
-
INTERRUPT SET AND FUNCTION
3
-51 -
2
Interrupt Source
No Interrupt pending
1. OER = 1
3. NSER = 1 4. SBD = 1
1. RBR data ready
2. FIFO interrupt active level
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
reached
1
0
2. PBER =1
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
Publication Release Date: April 2003
Clear Interrupt
Read USR
1. Read RBR
2. Read RBR until FIFO
data under active level
Read RBR
W83977EF
-
Revision 1.1