tc94a23f TOSHIBA Semiconductor CORPORATION, tc94a23f Datasheet - Page 12

• Manufacturer Part Number: tc94a23f
• Description: Single-chip Cd Processor With Built-in Controller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Number
Pin
81
82
83
84
85
86
87
90
91
Symbol
HOLD
DV
DV
DV
DV
DV
RST
RO
LO
SR
RR
DD
RL
SL
CD processor control
Hold mode control
input/output
Reset input
Pin Name
input
R-channel D/A converter block ground pin
R-channel data forward rotation output pin
R-channel reference voltage pin
D/A converter block power supply pin
L-channel reference voltage pin
L-channel data forward rotation output pin
L-channel D/A converter block ground pin
Device system reset signal input pin.
While the RST is at Low level, reset is
applied. When the RST is at High level, the
CD block is in operation, and the controller
program starts from address 0.
Normally, when 2.7 V or higher voltage is
supplied to the MV
reset is applied (power-on reset). Fix the pin
to High level.
Input pin used to request or release hold
state.
Normally, the pin is used for inputting the CD
mode selection signal or battery detection
signal.
Halt states are Clock Stop mode (crystal
oscillator stops oscillation) and Wait mode
(CPU stops). The modes are entered using
the CKSTP and WAIT instructions.
By program, Clock Stop mode can be entered
by detection of Low level on the HOLD pin or
by forced execution. Clock Stop mode can be
released by detection of High level on the
HOLD pin or change in the HOLD pin input.
Executing the CKSTP instruction stops the
clock generator and the CPU, entering
memory backup state. During memory backup
state, current dissipation becomes low (1 mA
or below). The display output and CMOS
output port automatically become Low level.
The N-channel open drain output becomes
off.
Regardless of the HOLD pin input state, Wait
mode is executed and current dissipation
becomes low. Crystal oscillator only on or
CPU operation suspended can be
programmed. When the crystal oscillator only
is on, all displays are at Low level. The other
pins are in Hold state. When CPU operation is
suspended, all states are held except that the
CPU is suspended. Wait mode is released by
a change of the HOLD pin input.
(Note)
To use Backup mode, turn off the
V
enter Backup mode.
DD
Function and Operation
12
pin (power supply for CD), and
DD
when at 0 V, system
DV
DV
RO/LO
RR
SL
/DV
/DV
SR
RL
Remarks
DV
TC94A23F
DD
2002-02-06
DV
MV
DD
MV
V
SS
DD
DD