tc94a04afdg TOSHIBA Semiconductor CORPORATION, tc94a04afdg Datasheet
tc94a04afdg
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tc94a04afdg Summary of contents
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... The microcontroller interface can be selected between Toshiba original 3 line mode and I • CMOS silicon structure supports high speed. • Power supply is a single 5 V. • The package are 60-pin and 80 pin flat package. TC94A04AFG/AFDG TC94A04AFG P-QFP60-1414-0.80N TC94A04AFDG P-QFP80-1420-0.80M Weight P-QFP60-1414-0.80N : 1.08 g (typ.) P-QFP80-1420-0.80M: 1.57 g (typ mode. 1 2005-09-28 ...
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Block Diagram/Pin Connection TC94A04AFG LIN4 19 kΩ C1 Lch input 46 C1 Mute SW LIN3 19 kΩ LIN2 19 kΩ kΩ LIN1 19 kΩ RIN4 50 VRAL ...
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... TC94A04AFDG LIN4 19 kΩ C1 Lch input 65 C1 Mute SW LIN3 C2 19 kΩ LIN2 19 kΩ kΩ 67 500 Ω C3 LIN1 19 kΩ RIN4 69 VRAL RIN3 70 Rch input RIN2 500 Ω 71 Same as Lch input circuit RIN1 GNDAL 74 OUTL 27 kΩ ...
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... Note pin (TC94A04AFG): Input level changes TTL/CMOS level by the command (42h: VS). Output is fixed to CMOS level. In case of TC94A04AFDG, pin number are pins and pins. Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to V GND. 6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56 64, 73, 77 pins. Function ...
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... Note pin (TC94A04AFG): Input level changes TTL/CMOS level by the command (42h: VS). Output is fixed to CMOS level. In case of TC94A04AFDG, pin number are pins and pins. Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to V GND. 6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56 64, 73, 77 pins. TC94A04AFG/AFDG ...
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... RST Reset pin. “L” at initialization. Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to V GND. 6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56 64, 73, 77 pins. Function Master clock is 768 fs. Each master-clock frequency follows. ...
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... OUTR (59 pin RIN1 Omitted 1 Note 3: In case of TC94A04AFDG, these are NC pins as below. Normally open, otherwise it connects to V GND. 6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56 64, 73, 77 pins. TC94A04AFG/AFDG Function Transmission Mode Toshiba original bus mode 2 I ...
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Microcontroller Interface 2.1 Standard Transmission Mode When I2CS = “L”, data can be transmitted or received in Standard Transmission mode. When the CS signal is Low, control from the microcontroller is enabled. The IFCK signal is the transmit/receive clock. ...
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Setting RAM (sequential) CS IFCK IFDI A15 Don’t care A14 The RAMs are set by command data using the IFDI signal. The first byte is a command, which differs for each ...
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Setting RAM (ACMP mode) CS IFCK IFDI A15 Don’t care A14 In ACMP mode, the TC94A04AFG/AFDG does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). In this ...
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I C Bus Mode When I2CS = “H”, data can be transmitted or received in I When the CS signal is Low, control from the microcontroller is enabled mode, the CS signal can be ...
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Setting RAM (sequential) start 32h HZ CS IFCK IFDI (MCU → The RAMs are set by command data using the IFDI signal. 2 The first byte after the ...
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Setting RAM (ACMP mode) start 32h HZ CS IFCK IFDI (MCU → ACMP mode, the TC94A04AFG/AFDG does not write data directly to coefficient RAM (CRAM) or offset RAM (OFRAM). ...
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Control Commands The following table lists the control commands that can be used from the microcontroller. 3.1 Control-Command Table Table 1 Control commands Command Code R/W TIMING 40h Timing BOOT 41h Self boot ROM start address DIN/AIN 42h Setting ...
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Control Commands Description Each command explanation is shown below. * mark in each command explanation table shows the initial value at the time of reset. Command-40h (0100 0000): TIMING (4400h*) D15 D14 D13 D12 D11 0 SYPD SYD1 SYD0 ...
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Command-41h (0100 0001): BOOT (0000h*) D15 D14 D13 D12 D11 Bit Name Description D15 ⎯ to Fixed to 0 (zero BTA to Self-boot ROM start address [8:0] D0 Command-42h (0100 0010): DIN/AIN (0100h*) ...
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Command-43h (0100 0011): DOUT/AOUT (0080h*) D15 D14 D13 D12 D11 HSMP 0 Bit Name Description D15 ⎯ to Fixed to 0 (zero) D13 Switching high sampling of D12 HSMP analog output D11 ⎯ Fixed to 0 (zero) ...
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Command-44h (0100 0100): RUN-MUTE (1F0Fh*) D15 D14 D13 D12 D11 AD RUN 0 0 IMUTE MUT Bit Name Description D15 RUN ASP program execution D14 ⎯ Fixed to 0 (zero) D13 D12 ADMUT ADC mute D11 IMUTE ASP block input ...
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Command-45h (0100 0101): MSEQ D15 D14 D13 D12 D11 Bit Name Description D15 ⎯ to Fixed to 0 (zero MSA Module sequential RAM first to address [2:0] D0 D15 D14 D13 D12 D11 ...
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Command-46h (0100 0110): CRAM D15 D14 D13 D12 D11 Bit Name Description D15 ⎯ to Fixed to 0 (zero CRAMA CRAM (coefficient RAM) head to address [8:0] D0 D15 D14 D13 D12 D11 ...
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Command-47h (0100 0111): CRAM-ACMP D15 D14 D13 D12 D11 Bit Name Description D15 ⎯ to Fixed to 0 (zero CRAMA CRAM (coefficient RAM) head to address [8:0] D0 D15 D14 D13 D12 D11 ...
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Command-48h (0100 1000): ORAM D15 D14 D13 D12 D11 Bit Name Description D15 ⎯ to Fixed to 0 (zero ORAMA ORAM (offset RAM) head to address [3:0] D0 D15 D14 D13 D12 D11 ...
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Command-49h (0100 1001): ORAM-ACMP D15 D14 D13 D12 D11 Bit Name Description D15 ⎯ to Fixed to 0 (zero ORAMA ORAM (offset RAM) head to address [3:0] D0 D15 D14 D13 D12 D11 ...
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Command-4Ah (0100 1010): IFF (0000h*) D15 D14 D13 D12 D11 Bit Name Description D15 ⎯ to Fixed to 0 (zero) D4 Set IFFn ( IFF2 Command-4Bh (0100 1011): DE-EMPH (0000h*) ...
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Command-4Dh (0100 1101): DAC-CS (1F1Fh*) D15 D14 D13 D12 D11 ATTC ATTC Bit Name Description D15 ⎯ to Fixed to 0 (zero) D13 D12 ATTC to DAC C-ch attenuator value [4: ⎯ to ...
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Command-4Fh (0100 1111): M-RST (0000h*) D15 D14 D13 D12 D11 MRST Bit Name Description Initialization from the micro D15 MRST controller command D14 ⎯ to Fixed to 0 (zero) D0 D10 ...
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Self-Boot Function Description 4.1 Self-Boot Function The TC94A04AFG/AFDG supports a self-boot function for setting coefficients and offsets. As Figure 1 shows, the data are set via the microcontroller interface circuit. First saving the data to be set via the ...
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Boot ROM Format The following shows the breakdown of the 18 bits. 00 Data that are being sent 01 Command 10 Final data (after the data are sent, the CS signal set to “H”). 11 Jump address (jump to ...
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Self-Boot Operation Self-boot operation supports two modes: one for use at reset and for setting the microcontroller. 4.3.1 Self-Boot Operation at Reset To enter this mode, set the RST pin to High or send initialized command. The 2048 fs ...
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Cautions on Use 5.1 Initial Reset After a power-supply injection, once at least, please set up a required register after applying reset which makes RST terminal “L” level and making the value of an internal register decide. 5.2 The ...
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... Maximum Ratings Characteristics Power supply voltage Input voltage TC94A04AFG Power dissipation TC94A04AFDG Operating temperature Storage temperature Note 8: Power dissipation of TC94A04AFG is reference value when assembled chip on PCB. (normally 1250 mW.) Electrical Characteristics (unless otherwise specified 25° Characteristics Characteristics ...
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Input Pins Characteristics Symbol “H” level Input voltage (2) “L” level “H” level Input voltage (3) “L” level “H” level Input leakage current “L” level Note 9: SYNC, ELRI/O, EBCI/O, DIN0 to 2 Note 10 IFCK, IFDI, I2CS, ...
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AC Characteristics AD Converter: LIN1 to LIN4, RIN1 to RIN4 Pins Characteristics Symbol Maximum input signal level Input impedance S/N S/( ratio S/N THD + N THD Cross-talk Dynamic range Note 15: One input pin selected of four ...
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Timing Clock Input Pin (XI) Characteristics Symbol Clock cycle Clock “H” cycle width Clock “L” cycle width Reset Pin ( RST ) Characteristics Symbol Standby time Reset pulse width t Audio Serial Interface (EBCI/O, ELRI/O, DIN0 to 2, DOUT) Characteristics ...
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Microcontroller Interface (1) Standard transmission mode ( CS , IFCK, IFDI, IFDO) Characteristics Symbol Standby time CS ↓ -IFCK ↓ setup time IFCK “L” cycle width IFCK “H” cycle width t IFCK ↑ ↑ setup time CS “H” ...
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AC Characteristic Measurement Point (1) Clock pin (XI) XI 50% (2) Reset 100% 90 RST (3) Audio serial interface (ELRI/O, EBCI/O, DIN0 to 2, DOUT) t EBIL ELRI/O (I) EBCI/O (I) DIN0 ∼ LIH t ...
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Microcontroller interface in standard transmission mode ( CS , IFCK, IFDI, IFDO) RST CS t STB t t CCD WLC CS IFCK IFDI t SCD IFDO t DDO (5) Microcontroller interface BUF IFDI IFCK t t ...
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Peripheral Circuit Example 1 The circuit below is an example circuit only. The operation of this circuit is not guaranteed by Toshiba. 4.7 µF 1 kΩ Lch (LIN4) 2200 pF 4.7 µF 1 kΩ Rch (RIN4) 2200 pF 4.7 µF ...
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... Rch (RIN1) 2200 pF OUTL 10 µF OUTR 10 µ LIN4 66 LIN3 67 LIN2 68 LIN1 69 RIN4 70 RIN3 71 RIN2 72 RIN1 TC94A04AFDG (top view GNDAL 75 OUTL 47 µF 76 VRAL DALR 47 µF 79 VRAR 80 OUTR 0.1 µ ...
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Package Dimensions Weight: 1.08 g (typ.) (Note) Palladium plate 40 TC94A04AFG/AFDG 2005-09-28 ...
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Package Dimensions Weight: 1.57 g (typ.) TC94A04AFG/AFDG (Note) Palladium plate it 2005-09-28 ...
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TC94A04AFG/AFDG 42 2005-09-28 ...