lm8850urx National Semiconductor Corporation, lm8850urx Datasheet - Page 11

• Manufacturer Part Number: lm8850urx
• Description: High-performance, Step-up Dc-dc Converter For High- Power Applications In Mobile Devices
• Manufacturer: National Semiconductor Corporation

I
START and STOP bits classify the beginning and the end of
the I
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. All
clock pulses are generated by the master. The transmitter re-
leases the SDA line (HIGH) during the acknowledge clock
pulse. The receiver must pull down the SDA line during the
ninth clock pulse, signifying an acknowledge. A receiver
which has been addressed must generate an acknowledge
after each byte has been received.
w = write (SDA = “0”)
r = read (SDA = “1)
ack = acknowledge (SDA pulled down by either master or
slave)
rs = repeated start
id = chip address
2
C START AND STOP CONDITIONS
2
C session. START condition is defined as SDA signal
2
C master always generates
START and STOP Conditions
I
2
I
C Chip Address
2
C Write Cycle
11
START and STOP bits. The I
after START condition and free after STOP condition. During
data transmission, I
conditions. First START and repeated START conditions are
equivalent, function-wise.
After the START condition, the I
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LM8850 address
is 0x60. the eighth bit, a “0” indicates a WRITE and a “1” in-
dicates a READ. The second byte selects the register to which
the data will be written. The third byte contains data to write
to the selected register.
Chip address: 60h
2
C master can generate repeated START
30113216
2
C bus is considered to be busy
2
C master sends a chip ad-
30113213
30113214
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