cat64lc40 Catalyst Semiconductor, cat64lc40 Datasheet
cat64lc40
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cat64lc40 Summary of contents
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... Ready/BUSY Status © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice DESCRIPTION The CAT64LC40 is a 4K-bit Serial EEPROM which is configured as 256 registers by 16 bits. Each register can be written (or read) serially by using the DI (or DO) pin. The CAT64LC40 is manufactured using Catalyst’s advanced CMOS EEPROM floating gate technology ...
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... CAT64LC40 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with (1) Respect to Ground ............ –2. with Respect to Ground ............... –2.0V to +7.0V CC Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C ...
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... – 2.5V V – 0.3 CC 6.0V V – 0.3 CC 2.4 2.5V 0.4 6.0V 0.4 3 CAT64LC40 Test Conditions Units f = 250 kHz MHz µ GND µ GND µ GND to V OUT –10µA ...
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... CAT64LC40 A.C. OPERATING CHARACTERISTICS V = +2.5V to +6.0V, unless otherwise specified. CC Symbol Parameter CS Setup Time t CSS CS Hold Time t CSH t DI Setup Time DIS t DI Hold Time DIH t Output Delay to 1 PD1 t Output Delay to 0 PD0 (2) t Output Delay to High Impendance HZ Minimum CS High Time t CSMIN t Minimum SK High Time ...
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... 10100100 10100011 10100000 10100001 (2)(3)( 100 pF 0 0.3 x 0.8. x 0.3 and CAT64LC40 Data D15 - D0 D15 - D0 D15–D0 REFERENCE POINTS Doc. No. 1021, Rev. A ...
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... DEVICE OPERATION The CAT64LC40 is a 4K-bit nonvolatile memory in- tended for use with all standard controllers. The CAT64LC40 is organized in a 256 x 16 format. All instructions are based on an 8-bit format. There are four 16-bit instructions: READ, WRITE, EWEN, and EWDS. The CAT64LC40 operates on a single power supply ranging from 2 ...
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... The CAT64LC40 requires an active LOW CS in order to be selected. Each instruction must be preceded by a HIGH-to-LOW transition of CS before the input of the 4- bit start sequence. Prior to the 4-bit start sequence (1010), the device will ignore inputs of all other logical sequence ...
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... CAT64LC40 WRITE cycle. The RDY/BSY pin will output the BUSY status (LOW) one t after the rising edge of the 32nd SV clock (the last data bit) and will stay LOW until the write cycle is complete. Then it will output a logical “1” until the next WRITE cycle ...
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... Catalyst Semiconductor, Inc. Characteristics subject to change without notice ERASE/WRITE ENABLE and DISABLE The CAT64LC40 powers up in the erase/write disabled state. After power-up or while the device erase/ write disabled state, any write operation must be pre- ceded by an execution of the EWEN instruction. Once enabled, the device will stay enabled until an EWDS has been executed or a power-down has occured ...
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... CAT64LC40 ORDERING INFORMATION 64LC40 Notes: (1) The device used in the above example is a 64LC40SI-TE13 (SOIC, Industrial Temperature, Tape & Reel) Doc. No. 1021, Rev PDIP S: SOIC (JEDEC) J: SOIC (JEDEC) U: TSSOP UR: TSSOP (Rotated) L: PDIP (Lead free, Halogen free) V: SOIC (JEDEC) (Lead free, Halogen free) ...
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... Catalyst Semiconductor, Inc. Characteristics subject to change without notice (1.78 TYP) 0.42 TYP 0 LAND PATTERN RECOMMENDATION ALL LEAD TIPS (0.9) 0.10 + 0.05 TYP 0.19 - 0.30 TYP 0 CAT64LC40 7.72 TYP 4.16 TYP 0.65 TYP SEE DETAIL A 0.09 - 0.20 TYP GAGE PLANE 0.25 0.6+0.1 SEATING PLANE DETAIL A Doc. No. 1021, Rev. A ...
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... Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. ...