lm9627 National Semiconductor Corporation, lm9627 Datasheet - Page 15

• Manufacturer Part Number: lm9627
• Description: Color Cmos Image Sensor Vga 30 Fps
• Manufacturer: National Semiconductor Corporation

Functional Description
6.0
The LM9627 contains a clock generation module that will create
two clocks as follows:
7.0
A frame is defined as the time it takes to reset every pixel in the
array, integrate the incident light, convert it to digital data and
present it on the digital video port. This is not a concurrent pro-
cess and is characterized in a series of events each needing a
certain amount of time as shown in Figure 23.
7.1
Full frame integration is when each pixel in the array integrates
light incident on it for the duration of a frame (see Figure 24).
The number of Hclk clock cycles required to process & shift out
one row of pixels is given by:
Where:
Confidential
Hclk,
CLK
R
R
opcycle
delay
CLOCK GENERATION MODULE
FRAME RATE PROGRAMING
Full Frame Integration
pixel
Figure 23. Frame Readout Flow Diagram
the horizontal clock. This is an internal system
clock and can be programmed to be the input
clock (mclk) or mclk divided by any number
between 1 and 255.
the pixel clock. This is the external pixel clock
that appears at the digital video port. It can be
Hclk or Hclk divided by 2. This clock cannot be
programed.
is a fixed integer value of 780 representing the
Row Operation Cycle Time in multiples of Hclk
clock cycles. It is the time required to carry out
all fixed row operations outlined in Figure 23.
a programmable value between 0 & 2047 repre-
senting the Row Delay Time in multiples of Hclk.
This parameter allows the Row Operation Cycle
time to be extended. (See the Row Delay High
and Row Delay Low registers).
Yes
RN
Transfer all pixels to CDS
Hclk
Shift all pixels out of row
Reset all pixels in row
Row address = 0
= R
Row delay time
Row address + 1
opcycle
Last row?
Start
+ R
(continued)
delay
No
15
The number of rows in a scan window is given by:
Where:
The number of Hclk clocks required to process a full frame is
given by:
Where:
7.2
In some cases it is desirable to reduce the time during which the
pixels in the array are allowed to integrate incident light without
changing the frame rate.
This is known as Partial Fame Integration and can be achieved
by resetting pixels in a given row ahead of the row being
selected for readout as shown in Figure 24. The number of Hclk
clocks required to process a partial frame is given by:
Where:
The Integration time is subject to the following limits:
Progressive Scan
Interlace
Sub-Sampled
RAD
RAD
M
SWN
F
The frame rate is given by:
RN
I
time
delay
factor
FN
Partial Frame Integration
Hclk
end
start
Hclk
rows
Mode
Progressive Scan
Sub-sampling or Interlace
= [(M
SWN
is the end row address of the defined scan win-
dow. (See section 2.1)
is the start row address of the defined scan win-
dow. (Scan section 2.1).
is a Mode Factor which must be applied. It is
dependent on the selected mode of operation as
shown in the table below:
is the Number of Rows in Selected Scan Win-
dow.
a programmable value between 0 & 4097 repre-
senting the Inter Frame Delay in multiples of
RN
be extended. (See the Frame Delay High and
Frame Delay Low registers).
is the number of Hclk clock cycles required to
process & shift out one row of pixels.
is the number of rows ahead of the current row
to be reset. (See the Integration Time High and
Low registers).
Hclk
factor *
FP
rows
Frame Rate =
. This parameter allows the frame time to
Hclk
= (RAD
SWN
= RN
I
I
I
time <=
time <=
time <=
rows
end
Hclk *
) + F
- RAD
FN
Hclk
SWN
SWN
SWN
I
time
Hclk
delay
start
Limit
rows +
rows +
rows +
]
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) + 1
*
1
0.5
RN
F
2
0.5
*
delay
Hclk
F
*
delay
F
delay