bd9876efj ROHM Co. Ltd., bd9876efj Datasheet - Page 5

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bd9876efj

Manufacturer Part Number
bd9876efj
Description
Flexible Step-down Switching Regulator With Built-in Power Mosfet
Manufacturer
ROHM Co. Ltd.
Datasheet

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●Detailed Description
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BD9876EFJ
© 2011 ROHM Co., Ltd. All rights reserved.
◇Synchronizes to External Clock
◇SOFT START
◇OCP operation
The SYNC pin can be used to synchronize the regulator to an external system clock. To implement the synchronization
feature connect a square wave to SYNC pin. The square wave amplitude must transition lower than 0.8V and higher than
2.0V on the SYNC pin and have an on time greater than 100ns and an off time greater than 100ns. The synchronization
frequency range is 200 kHz to 500 kHz. The rising edge of the LX will be synchronized to the falling edge of SYNC pin
signal after SYNC input pulse 3 count. At the synchronization, the external clock is removed, the device transitions
self-running mode after 7 microseconds.
The soft start time of BD9876EFJ is determined by the DCDC operating frequency (self-run mode 300 kHz ⇒10ms).
If synchronization is used at the time of EN=ON, The soft start time is restricted by SYNC pin input pulse frequency.
SYNC pin input pulse frequency is fosc_ex kHz, the soft start time is expressed by below equation.
The device has the circuit of over current protection for protecting the FET from over current.
To detect OCP 2 times sequentially, the device will stop and after 13 msec restart.
SYNC
OCP_LATCH
SYNC_LATCH
Lx
VOUT
OCP
VC
Tss =
Lx
fosc_ex
300
output connect to GND
VC voltage rising by
× 10 [ms]
OCP threshold
Fig.4 Timing chart at OCP operation
Fig.3 Timing chart at Synchronization
the OCP current 2 times sequencially
force the High side FET OFF
(pulse by pulse protection)
output connect to GND
VC voltage discharged
set the OCP latch by detecting
by detecting OCP current
400nsec
by OCP latch
5/16
Set the latch for
synchronization
7µsec
about
OCP latch reset after 13 msec
(300kHz 4000 counts)
Technical Note
2011.07 - Rev.B

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