W83194R-37 Winbond Electronics Corp America, W83194R-37 Datasheet - Page 15

• Manufacturer Part Number: W83194R-37
• Description: Description = 100MHz/133MHz Via MVP3, Via Apollo Pro Clock Gen., 3-DIMM, With S.S.T. ;; Package = Ssop 48
• Manufacturer: Winbond Electronics Corp America

10.2 PCI_STOP# Timing Diagram
For synchronous Chipset, PCI_STOP# pin is a synchronous "active low" input pin used to stop the
PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock (PCICLK_F). All other clocks will continue to run while the
PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output with
full pulse width. In this case, PCI "clocks on latency" is less than 1 PCI clocks and clocks off latency is
less then 1 PCI clocks.
11.0 OPERATION OF DUAL FUCTION PINS
Pins 2, 7, 8, 25 and 26 are dual function pins and are used for selecting different functions in this
device (see Pin description). During power up, these pins are in input mode (see Figure 1), therefore,
and are considered input select pins. When V
pins are latched into their appropriate internal registers. Once the correct information are properly
latched, these pins will change into output pins and will be pulled low by default. At the end of the
power up timer (within 3 mS) outputs starts to toggle at the specified frequency.
PCI_STOP#
PCICLK[0:4]
PCICLK_F
CPUCLK
(Internal)
(Internal)
PCICLK
#2 REF0/CPU3.3#_2.5
#7 PCICLK_F/FS1
#8 PCICLK0/FS2
#25 24/MODE
#26 48/FS0
All other clocks
1
Output
tri-state
Output
tri-state
Input
2.5V
DD
2
reaches 2.5V, the logic level that is present on these
- 15 -
Preliminary W83194R-37/-58
Output
pull-low
Output
pull-low
Within 3 mS
Output
Publication Release Date: April 1999
1
2
V
DD
Revision A1