ml4813 Micro Electronics Corporation, ml4813 Datasheet - Page 6

• Manufacturer Part Number: ml4813
• Description: Flyback Power Factor Controller
• Manufacturer: Micro Electronics Corporation

ML4813
FUNCTIONAL DESCRIPTION
OSCILLATOR
The ML4813 oscillator charges the external capacitor (C
with a current (I
voltage reaches the upper threshold, the comparator
changes state and the capacitor discharges to the lower
threshold through Q1. While the capacitor is discharging,
Q2 provides a high pulse.
The oscillator period can be described by:
where:
and:
A graph showing the relationship between R
oscillator frequency, and maximum duty cycle is given in
Figure 1. A pulse of a duration shorter than t
from an external frequency source set to a higher
frequency than f
synchronize the oscillator. R
longer pulses, as shown in Figure 2.
OUTPUT DRIVER STAGE
The ML4813 output driver is a 1A peak output high speed
totem-pole circuit designed to quickly drive capacitive
loads such as MOSFET gates. See Figure 3 for the output
saturation characteristics for sourcing and sinking current.
ERROR AMPLIFIER
The ML4813 error amplifier is a high open loop gain,
wide bandwidth amplifier. See Figure 4 for the gain and
phase plot.
UN-COMMITTED OP-AMP
The ML4813 contains an uncommitted op amp which is
normally configured as a differencing amplifier to sense
the output voltage. The output voltage in the flyback
configuration is not ground referenced. The op amp in the
ML4813 is a PNP input amplifier similar to the LM324
but with an open emitter class A output stage.
REFERENCE
The reference output voltage versus output current
characteristic is shown in Figure 5.
UNDERVOLTAGE LOCKOUT
On power-up, the ML4813 is in the UVLO condition;
6
t
t
t
RAMP
DEADTIME
OSC
=
=
t
RAMP
I
C
SET
=
T
SET
8 4 .
OSC
+
) equal to 5/R
mA I
t
DEADTIME
C
can be applied to pin SYNC to
T
-
SET
SYNC
SET
and C
. When the capacitor
SYNC
T
DEADTIME
, C
shorten
T
, the
(1)
(2)
(3)
T
)
output low and quiescent current low. The ML4813
becomes operational when V
drops below 10V, the UVLO condition is re-imposed.
During UVLO, the V
"flag" for starting up a down-stream PWM converter.
EXTERNAL
CLOCK
RAMP VALLEY
Figure 1. Oscillator Timing Resistance vs. Frequency
RAMP PEAK
C SYNC
R SYNC
CLOCK
10
Figure 2. Oscillator Block Diagram
8
5
3
2
1
10
10nF
20nF
V(C T )
I SET
OSCILLATOR FREQUENCY (kHz)
C T
R T
REF
5nF
pin is off, making it usable as a
10
16
2nF
9
SYNC
R T
C T
8.4mA
CC
T D
100
reaches 16V. When V
I SET
1nF
5.6V
90%
+
-
1000
85%
80%
70%
CC