tmp88ch41ug TOSHIBA Semiconductor CORPORATION, tmp88ch41ug Datasheet - Page 141
tmp88ch41ug
Manufacturer Part Number
tmp88ch41ug
Description
8 Bit Microcontroller Tlcs-870/x Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP88CH41UG.pdf
(240 pages)
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tmp88ch41ug-7B64(JOA)
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Overload protection
setting current
Input MG pin
Input CL pin
PWM output
("H" active)
MG setting current
EMGCRA<CLCNT>. The sampling times can be set in the range of 1 to 15 times at 200 ns period
(when fc = 20 MHz). If a low level is detected as many times as the specified number, overload pro-
tection is assumed.
This facility allows selecting to disable no phases, all phases, PWM phases, or all upper phases/all
lower phases. When selected to disable all upper phases/all lower phases, port output is determined
by their turn-on status immediately before being disabled. When two or more upper phases are
active, all upper phases are turned on and all lower phases are turned off; when two or more lower
phases are active, all upper phases are turned off and all lower phases are turned on.
load protective circuit is disabled, overload protective interrupts (INTCLM) are not generated.
The number of times the overload protective input is sampled can be set by using the
The output disabled phases during overload protection are set by using the EMGCRB<CLMD>.
When output phase are cut off, output is inactive (low in the case of high active). When the over-
Figure 14-14 Example of Protection Circuit Operation
I (Current)
Overload protection
(Output cut off)
Page 131
(High-Z output)
MG protection
TMP88FH41UG
t (time)
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