tmp88ch40img TOSHIBA Semiconductor CORPORATION, tmp88ch40img Datasheet - Page 25

• Manufacturer Part Number: tmp88ch40img
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.1.5 Reset Circuit
2.1.5.1
2.1.5.2
timer reset, or system clock reset.
reset) are not initialized.
Table 2-2 Internal Hardware Initialization by Reset Operation
The TMP88CH40IMG has four ways to generate a reset: external reset input, address trap reset, watchdog
Table 2-2 shows how the internal hardware is initialized by reset operation.
At power-on time, the internal cause reset circuits (watchdog timer reset, address trap reset, and system clock
Program Counter (PC)
Stack Pointer (SP)
General-purpose Registers
(W, A, B, C, D, E, H, L)
Register Bank Selector (RBS)
Jump Status Flag (JF)
Zero Flag (ZF)
Carry Flag (CF)
Half Carry Flag (HF)
Sign Flag (SF)
Overflow Flag (VF)
Interrupt Master Enable Flag (IMF)
Interrupt Individual Enable Flag (EF)
Interrupt Latch (IL)
Interrupt Nesting Flag (INF)
at least three machine cycles (12/fc [s]) or more while the power supply voltage is within the rated operat-
ing voltage range and the oscillator is oscillating stably, the device is reset and its internal state is initial-
ized.
program beginning with the vector address stored at addresses FFFFCH to FFFFEH.
internal RAM,SFR or DBR area, the device generats an internal reset.
The address trap is permited initially and the internal reset is generated by fetching from internal
RAM,SFR or DBR area. If the address trap is prohibited, instructions in the internal RAM area can be
executed.
External Reset Input
Adress Trap Reset
The
When the
If the CPU should start looping for reasons of noise, etc. and attempts to fetch instructions from the
The addess trap permission/prohibition is set by the address trap reset control register (ATAS,ATKEY).
Internal Hardware
RESET
RESET
pin is a hysteresis input with a pull-up resistor included. By holding the
pin input is released back high, the device is freed from reset and starts executing the
RESET
Figure 2-9 Reset Circuit
(FFFFEH to FFFFCH)
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Not initialized
Initial Value
0
1
0
0
0
0
VDD
Page 17
RAM
Prescaler and divider for the
timing generator
Watchdog timer
Output latch of input/output port
Control register
Internal Hardware
Reset input
Not initialized
See description of
each input/output
port.
See description of
each control
register.
Initial Value
Enable
0
TMP88CH40IMG
RESET
pin low for