tb6560aftg TOSHIBA Semiconductor CORPORATION, tb6560aftg Datasheet - Page 20

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tb6560aftg

Manufacturer Part Number
tb6560aftg
Description
Pwm Chopper-type Bipolar Driver Ic For Stepping Motor Control
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
13. CLK and Internal OSC Signals and Output Current Waveform
(when the CLK signal is asserted during Slow Decay mode)
When the CLK signal is asserted, the Chopping Counter (OSC Counter) is forced to reset at the next rising
edge of the OSC signal.
As a result, the response to input data is faster compared to methods in which the counter is not reset.
The delay time that is theoretically determined by the logic circuit is one OSC cycle = 10 μs at a 100-kHz
chopping rate.
After the OSC Counter is reset by the CLK signal input, the current control mode is invariably switched to
Charge mode briefly for current sensing.
Note: Even in Fast Decay mode, the current control mode is invariably switched to Charge mode briefly for
OSC Pin Internal
Waveform
Predefined
Current Level
I
OUT
current sensing.
CLK Signal Input
f
chop
NF
The CR counter is reset here.
25 % Mixed Decay Mode
Current Level
Predefined
f
chop
20
MDT
Switches to Charge mode briefly
RNF
NF
f
chop
MDT
TB6560AFTG
RNF
2011-05-23

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