ncv87706ds50r4g ON Semiconductor, ncv87706ds50r4g Datasheet - Page 10

• Manufacturer Part Number: ncv87706ds50r4g
• Description: Ncv8770 - Low Dropout Regulator With Reset
• Manufacturer: ON Semiconductor

thermal shutdown and internal current limit. Typical
characteristics are shown in Figure 4 to Figure 21.
Input Decoupling (C
and should be connected close to the NCV8770 package.
Higher capacitance and lower ESR will improve the overall
line and load transient response.
appropriate input filter must be used in order to decrease
rising and/or falling edges below 50 V/ms for proper
operation. The filter can be composed of several capacitors
in parallel.
Output Decoupling (C
a minimum Equivalent Series Resistance (ESR) for the
output capacitor. Stability region of ESR vs Output Current
is shown in Figure 13. The minimum output decoupling
value is 1 mF and can be augmented to fulfill stringent load
transient requirements. The regulator works with ceramic
chip capacitors as well as tantalum devices. Larger values
improve noise rejection and load regulation transient
response.
Reset Operation
provide feedback to the microprocessor of an out of
regulation condition. The timing diagram of reset function
is shown in Figure 21. This is in the form of a logic signal on
RO. Output voltage conditions below the RESET threshold
cause RO to go low. The RO integrity is maintained down
to V
(RO) circuitry includes internal pull−up (30 kW) connected
to the output (V
Reset Delay Time Select
DT pin determines the available Reset Delay times. The part
is designed for use with DT tied to ground or V
be controlled by any logic signal which provides a threshold
between 0.8 V and 2 V. The default condition for an open DT
pin is the slower Reset time (DT = GND condition). Times
are in pairs and are highlighted in the chart below. Consult
factory for availability. The Delay Time select (DT) pin is
logic level controlled and provides Reset Delay time per the
chart. Note the DT pin is sampled only when RO is low, and
changes to the DT pin when RO is high will not effect the
reset delay time.
The NCV8770 regulator is self−protected with internal
A ceramic or tantalum 0.1 mF capacitor is recommended
If extremely fast input voltage transients are expected then
The NCV8770 is a stable component and does not require
A reset signal is provided on the Reset Output (RO) pin to
Selection of the NCV8770y devices and the state of the
out
= 1.0 V. For 5 V voltage option, the Reset Output
out
) No external pull−up is necessary.
in
)
out
)
APPLICATIONS INFORMATION
out
, but may
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10
NOTE:
Thermal Considerations
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the NCV8770 has good thermal conductivity through the
PCB, the junction temperature will be relatively low with
high power applications. The maximum dissipation the
NCV8770 can handle is given by:
NCV8770 soldered on 645 mm
dissipate up to 2.35 W (for D2PAK−5) when the ambient
temperature (T
PCB area. The power dissipated by the NCV8770 can be
calculated from the following equations:
or
NOTE:
RESET DELAY AND RESET THRESHOLD OPTIONS
NCV87701
NCV87702
NCV87703
NCV87704
NCV87705
NCV87706
NCV8770A
NCV8770B
NCV8770C
NCV8770D
NCV8770E
NCV8770F
As power in the NCV8770 increases, it might become
Since T
The timing values can be selected from the following list:
Items containing I
4, 8, 16, 32, 64, 128 ms. Contact factory for options not
included in ORDERING INFORMATION table on
following page.
J
P
V
is not recommended to exceed 150°C, then the
D
in(max)
+ V
A
) is 25°C. See Figure 22 for R
P
D
in
+
(
DT = GND
max
I
Reset
16 ms
32 ms
16 ms
16 ms
32 ms
16 ms
q
P
Time
8 ms
8 ms
4 ms
8 ms
8 ms
4 ms
@I
)
D(max)
q
+
can be neglected if I
out
T
I
J(max)
) I
) V
out
2
, 1 oz copper area, FR4 can
R
) I
out
qJA
DT = V
128 ms
128 ms
128 ms
128 ms
128 ms
128 ms
out
* T
Reset
32 ms
64 ms
32 ms
64 ms
Time
8 ms
8 ms
V
q
in
A
* V
out
I
out
out
out
>> I
Threshold
qJA
Reset
q
93%
93%
93%
93%
93%
93%
90%
90%
90%
90%
90%
90%
.
(eq. 1)
(eq. 2)
(eq. 3)
versus