ncv8772 ON Semiconductor, ncv8772 Datasheet - Page 11

• Manufacturer Part Number: ncv8772
• Description: Ncv8772 Ultra Low Iq 350 Ma Ldo Regulator With Enable And Reset
• Manufacturer: ON Semiconductor

thermal shutdown and internal current limit. Typical
characteristics are shown in Figure 4 to Figure 24.
Input Decoupling (C
and should be connected close to the NCV8772 package.
Higher capacitance and lower ESR will improve the overall
line and load transient response.
appropriate input filter must be used in order to decrease
rising and/or falling edges below 50 V/ms for proper
operation. The filter can be composed of several capacitors
in parallel.
Output Decoupling (C
a minimum Equivalent Series Resistance (ESR) for the
output capacitor. Stability region of ESR vs Output Current
is shown in Figure 13. The minimum output decoupling
value is 1 mF and can be augmented to fulfill stringent load
transient requirements. The regulator works with ceramic
chip capacitors as well as tantalum devices. Larger values
improve noise rejection and load regulation transient
response.
Enable Operation
threshold limits are covered in the electrical characteristics
table in this datasheet.
Reset Operation
provide feedback to the microprocessor of an out of
regulation condition. The timing diagram of reset function
is shown in Figure 24. This is in the form of a logic signal on
RO. Output voltage conditions below the RESET threshold
cause RO to go low. The RO integrity is maintained down
to V
(RO) circuitry includes internal pull−up (30 kW) connected
to the output (V
Reset Delay Time Select (D2PAK−7 only)
the DT pin determines the available Reset Delay times. The
part is designed for use with DT tied to ground or V
may be controlled by any logic signal which provides a
threshold between 0.8 V and 2 V. The default condition for
an open DT pin is the slower Reset time (DT = GND
condition). Times are in pairs and are highlighted in the chart
below. Consult factory for availability. The Delay Time
select (DT) pin is logic level controlled and provides Reset
Delay time per the chart. Note the DT pin is sampled only
The NCV8772 regulator is self−protected with internal
A ceramic or tantalum 0.1 mF capacitor is recommended
If extremely fast input voltage transients are expected then
The NCV8772 is a stable component and does not require
The Enable pin will turn the regulator on or off. The
A reset signal is provided on the Reset Output (RO) pin to
Selection of the NCV8772yD7S devices and the state of
out
= 1.0 V. For 5 V voltage option, the Reset Output
out
) No external pull−up is necessary.
in
)
out
)
APPLICATIONS INFORMATION
out
http://onsemi.com
, but
11
when RO is low, and changes to the DT pin when RO is high
will not effect the reset delay time.
NOTE:
Thermal Considerations
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the NCV8772 has good thermal conductivity through the
PCB, the junction temperature will be relatively low with
high power applications. The maximum dissipation the
NCV8772 can handle is given by:
NCV8772 soldered on 645 mm
dissipate up to 2.35 W when the ambient temperature (T
is 25°C. See Figure 25 for R
dissipated by the NCV8772 can be calculated from the
following equations:
or
RESET DELAY AND RESET THRESHOLD OPTIONS
(D2PAK−7)
NCV87721D7S
NCV87722D7S
NCV87723D7S
NCV87724D7S
NCV87725D7S
NCV8772AD7S
NCV8772BD7S
NCV8772CD7S
NCV8772DD7S
NCV8772ED7S
As power in the NCV8772 increases, it might become
Since T
The timing values can be selected from the following list:
4, 8, 16, 32, 64, 128 ms. Contact factory for other timing
combinations not included in the table.
J
P
is not recommended to exceed 150°C, then the
D
+ V
P
D
in
(
DT = GND
max
I
Reset
16 ms
32 ms
16 ms
32 ms
q
Time
8 ms
8 ms
4 ms
8 ms
8 ms
4 ms
@I
)
+
out
qJA
T
J(max)
) I
2
versus PCB area. The power
, 1 oz copper area, FR4 can
R
out
qJA
DT = V
128 ms
128 ms
128 ms
128 ms
* T
Reset
32 ms
64 ms
32 ms
64 ms
Time
8 ms
8 ms
V
in
A
* V
out
out
Threshold
Reset
93%
93%
93%
93%
93%
90%
90%
90%
90%
90%
(eq. 1)
(eq. 2)
A
)