aoz1092d Alpha & Omega Semiconductor, aoz1092d Datasheet - Page 10

• Manufacturer Part Number: aoz1092d
• Description: Ezbucktm 3a Simple Buck Regulator
• Manufacturer: Alpha & Omega Semiconductor

If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum capacitor or
aluminum electrolytic capacitor may also be used as
output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It can
be calculated by:
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
Loop Compensation
The AOZ1092D employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole and can
be calculated by:
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
where;
C
R
ESR
I
ΔV
f
f
CO_RMS
O
L
p1
Z1
Rev. 1.3 February 2009
is load resistor value, and
is the output filter capacitor,
CO
O
=
=
=
is the equivalent series resistance of output capacitor.
---------------------------------- -
2π
------------------------------------------------
2π C
ΔI
×
×
=
L
C
×
----------
1
ΔI
O
O
ESR
12
L
×
1
×
R
ESR
CO
L
CO
www.aosmd.com
The compensation design is actually to shape the
converter close loop transfer function to get desired gain
and phase. Several different types of compensation
network can be used for the AOZ1092D. For most cases,
a series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1092D, FB pin and COMP pin are the invert-
ing input and the output of internal transconductance
error amplifier. A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
where;
G
A/V,
G
C
The zero given by the external compensation network,
capacitor C
To design the compensation circuit, a target crossover
frequency f
crossover frequency is where control loop has unity gain.
The crossover frequency is also called the converter
bandwidth. Generally a higher bandwidth means faster
response to load transient. However, the bandwidth
should not be too high because of system stability
concern. When designing the compensation loop,
converter stability under all line and load condition must
be considered.
Usually, it is recommended to set the bandwidth to be
less than 1/10 of switching frequency. The AOZ1092D
operates at a fixed switching frequency range from
400kHz to 600kHz. It is recommended to choose a
crossover frequency less than 50kHz.
The strategy for choosing R
cross over frequency with R
zero with C
to calculate R
f
f
f
R
p2
EA
VEA
C
Z2
C
C
is cthe compensation capacitor.
is the error amplifier transconductance, which is 200 x 10
=
=
=
is the error amplifier voltage gain, which is 500 V/V, and
=
50kHz
------------------------------------------ -
2π C
-----------------------------------
2π
f
C
×
C
C
×
C
×
. Using selected crossover frequency, f
for close loop must be selected. The system
--------- -
V
and resistor R
C
C
V
G
1
FB
:
C
C
O
EA
×
×
×
G
R
----------------------------- -
G
C
VEA
2π
EA
×
×
C
C
C
G
C
, is located at:
O
and C
and set the compensator
CS
C
is to set the
AOZ1092D
Page 10 of 16
C
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