a4935 Allegro MicroSystems, Inc., a4935 Datasheet - Page 24

• Manufacturer Part Number: a4935
• Description: Automotive 3-phase Mosfet Driver
• Manufacturer: Allegro MicroSystems, Inc.

9.00 ±0.20 7.00 ±0.20
A4935
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
Copyright ©2007-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
48X
0.08
C
0.22 ±0.05
48
A
1
2
B
9.00 ±0.20
7.00 ±0.20
Package JP 48-Pin LQFP with Exposed Thermal Pad
5.00
0.50
For the latest version of this document, visit our website:
5.00
www.allegromicro.com
0.10 ±0.05
1.40 ±0.05
Automotive 3-Phase MOSFET Driver
SEATING
PLANE
1.60 MAX
0.25
C
GAGE PLANE
7º
4° ±4
0º
SEATING PLANE
0.60 ±0.15
0.15
(1.00)
+0.05
–0.06
A
B
For Reference Only
(reference JEDEC MS-026 BBCHD)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Terminal #1 mark area
Exposed thermal pad (bottom surface)
Reference land pattern layout (reference IPC7351
QFP50P900X900X160-48M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
48
1.70
1
C
2
PCB Layout Reference View
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
C
5.00
8.60
0.30
0.50
5.00
8.60
24