ncp360 ON Semiconductor, ncp360 Datasheet - Page 8

• Manufacturer Part Number: ncp360
• Description: Usb Positive Ovp Pmosfet And Status Flag
• Manufacturer: ON Semiconductor

In Operation
voltage, up to 20 V. A PMOS FET protects the systems
(i.e.: VBUS) connected on the V
over-voltage. The Output follows the VBUS level until
OVLO threshold is overtaken.
Undervoltage Lockout (UVLO)
device has a built-in undervoltage lock out (UVLO)
circuit. During V
disconnected from input until V
nominal. The FLAGV output is pulled to low as long as V
does not reach UVLO threshold. This circuit has a 50 mV
hysteresis to provide noise immunity to transient condition.
Overvoltage Lockout (OVLO)
overvoltage, the device has a built-in overvoltage lock out
(OVLO) circuit. During overvoltage condition, the output
remains disabled until the input voltage exceeds OVLO -
Hysteresis.
OVLO. This circuit has a 100 mV hysteresis to provide
noise immunity to transient
FLAG Output
systems that a fault has occurred.
exceeded When V
FLAG is held high. The pin is an open drain output, thus a
pull up resistor (typically 1 MW- Minimum 10 kW) must
be provided to V
V
NCP360 provides overvoltage protection for positive
To ensure proper operation under any conditions, the
OVLO
UVLO
OVLO
UVLO
To protect connected systems on V
FLAG output is tied to low until V
NCP360 provides a FLAG output, which alerts external
This pin is tied to low as soon the OVLO threshold is
in
20 V
V
(V)
out
0
0
Figure 18. Output Characteristic vs. V
in
battery
positive going slope, the output remains
in
. FLAG pin is an open drain output.
level recovers normal condition,
conditions.
in
out
voltage is above 3.2 V
pin, against positive
in
is higher than
out
in
pin from
http://onsemi.com
NCP360
in
8
EN Input
to low or connected to ground. A high level on the pin
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
Internal PMOS FET
systems,
overvoltage. Regarding electrical characteristics, the
R
V
Figure 16).
ESD Tests
pin, 1 mF mounted on board).
protected input. In Contact condition, V
protected input.
electrostatic discharge waveform.
PCB Recommendations
the PCB rules must be respected to properly evacuate the
heat out of the silicon. The UDFN PAD1 must be connected
to ground plane to increase the heat transfer if necessary
from an application standpoint. Of course, in any case, this
pad shall be not connected to any other potential.
DSon
out
To enable normal operation, the EN pin shall be forced
NCP360 includes an internal PMOS FET to protect the
NCP360 fully support the IEC61000-4-2, level 4 (Input
That means, in Air condition, V
Please refer to Fig 19 to see the IEC 61000-4-2
The NCP360 integrates a 500 mA rated PMOS FET, and
pin, characterized by V
, during normal operation, will create low losses on
connected on OUT pin, from positive
Figure 19.
in
versus V
in
has a ±15 kV ESD
in
out
has ±8 kV ESD
dropout. (See