ncp3101c ON Semiconductor, ncp3101c Datasheet - Page 17

• Manufacturer Part Number: ncp3101c
• Description: Ncp3101c Wide Input Voltage Synchronous Buck Converter
• Manufacturer: ON Semiconductor

P
V
Control Dissipation
determined by the formula below:
I
P
V
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient temperature. The formula for calculating the
junction temperature with the package in free air is:
P
R
T
T
should be performed to ensure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow,
maximum input voltage, maximum loading, and component
variations (i.e., worst case MOSFET R
Compensation Network
network around the transconductance amplifier must be
used in conjunction with the PWM generator and the power
stage. Since the power stage design criteria is set by the
application, the compensation network must correct the
overall output to ensure stability. The output inductor and
capacitor of the power stage form a double pole at the
frequency shown in Equation 36:
C
F
L
The ESR of the output capacitor creates a “zero” at the
frequency a shown in Equation 37:
CC
BODY
C
D
A
LC
J
OUT
FD
CC
qJC
OUT
The control portion of the IC power dissipation is
Once the IC power dissipations are determined, the
As with any power design, proper laboratory testing
To create a stable power supply, the compensation
2.35 kHz +
F
LC
= Power dissipation of the IC
= Thermal resistance junction−to−case of
= Ambient temperature
= Junction temperature
= Output capacitor
= Double pole inductor and capacitor
= Output inductor value
= Low−side MOSFET body diode losses
= Control power dissipation
= Input voltage
= Body diode forward voltage drop
= Control circuitry current draw
+
MOSFET turning off and the high−side
MOSFET turning on, typically 42 ns
the regulator package
frequency
T
2p * 5.6 mH * 820 mF
2p * L
J
P
+ T
C
+ I
A
OUT
) P
1
CC
1
* C
* V
D
@ R
OUT
CC
qJC
³
DS(on)
).
(eq. 34)
(eq. 35)
(eq. 36)
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17
CO
C
F
power stage has created or open loop response of the system.
The next step is to close the loop by considering the feedback
values. The closed loop crossover frequency should be
greater then the F
frequency, which would place the maximum crossover
frequency at 55 kHz. Further, the calculated F
should meet the following:
F
F
not provide stability, and the output power stage must be
modified.
amplifier.
amplifier and the impedance networks Z
C
network has to provide a closed loop transfer function with
the highest 0 dB crossing frequency to have fast response
and the highest gain in DC conditions to minimize the load
regulation issues. A stable control loop has a gain crossing
with −20 dB/decade slope and a phase margin greater than
45°. Include worst−case component variations when
LC
SW
ESR
OUT
F
Figure 29. Pseudo Type III Transconductance Error
The two equations above define the bode plot that the
If the criteria is not met, the compensation network may
Figure 29 shows a pseudo Type III transconductance error
The compensation network consists of the internal error
) and external Z
ESR
RC
CC
16.2 kHz +
ZFB
F
ESR
= Switching frequency
= Output capacitor ESR zero frequency
CP
= Output capacitor ESR
= Output capacitor
= Output capacitor ESR frequency
+
2p * 12 mW * 820 mF
2p * CO
LC
FB
(R
F
and less than 1/5 of the switching
ESR
C
Amplifier
, C
ESR
1
1
+t
C
Gm
IEA
* C
, and C
VREF
F
OUT
SW
5
³
³
P
). The compensation
IN
(R
R 1
ESR
1
, R
ZIN
R 2
frequency
2
, R
(eq. 37)
(eq. 38)
CF
RF
F
, and