lt3742 Linear Technology Corporation, lt3742 Datasheet - Page 18

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lt3742

Manufacturer Part Number
lt3742
Description
Dual, 2-phase Step-down Switching Controller
Manufacturer
Linear Technology Corporation
Datasheet

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LT3742
APPLICATIONS INFORMATION
Bias Supply Considerations
The LT3742 uses an internal boost regulator to provide a
bias rail for enhancement of the external MOSFETs. This
bias rail is regulated to V
tion before either controller is allowed to start switching.
As this is a high speed switching regulator, standard
procedures must be followed regarding placement of the
external components. The SWB node should be kept small
to reduce EMI effects and the bias decoupling capacitor
(C
slight surplus of power is available from this supply and
it can be tapped after stringent engineering evaluation.
PC Board Layout Considerations
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
18
BIAS
Place the power components close together with short
and wide interconnecting traces. The power compo-
nents consist of the top MOSFETs, catch diodes and
the inductors C
is to simply place them on the board fi rst.
) should be kept close to the BIAS pin and V
IN
and C
IN
OUT
+ 7V and must be in regula-
. One way to approach this
IN
. A
Demo board gerber fi les are available to assist with a
reliable layout. It will be diffi cult to achieve data sheet
performance specifi cations with improper layout.
Similar attention should be paid to the power compo-
nents that make up the boost converter. They should also
be placed close together with short and wide traces.
Always use a ground plane under the switching regulator
to minimize interplane coupling.
Minimize the parasitic inductance in the loop of C
MOSFET and catch diode, which carry large switching
currents.
Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI low.
Use planes for V
fi ltering and to keep power losses low. Unused areas
can be fi lled with copper and connect to any DC node
(V
Place C
Keep the high dv/dt nodes (SW1, SW2, G1, G2, C
C
IN2
IN
, V
, SWB) away from sensitive small-signal nodes.
OUT
B
close to BIAS pin and input capacitor.
, GND).
IN
and V
OUT
to maintain good voltage
IN1
3742f
IN
,
,

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