lt3580ems8e-trpbf Linear Technology Corporation, lt3580ems8e-trpbf Datasheet - Page 16

• Manufacturer Part Number: lt3580ems8e-trpbf
• Description: Boost/inverting Dc/dc Converter With 2a Switch, Soft-start, And Synchronization
• Manufacturer: Linear Technology Corporation

LT3580
APPLICATIONS INFORMATION
tion, so they should not be used for calculating effi ciency
in discontinuous mode or at light load currents.
where:
Example: boost confi guration, V
= 0.5A, f = 1.25MHz, V
Thermal resistance for the LT3580 is infl uenced by the pres-
ence of internal, topside or backside planes. To calculate
die temperature, use the appropriate thermal resistance
number and add in worst-case ambient temperature:
where T
ture, θ
35°C/W to 40°C/W for the MSOP Exposed Pad package.
P
16
TOT
R
DC = duty cycle (see the Power Switch Duty Cycle
section for formulas)
η = power conversion effi ciency (typically 88% at high
currents)
I
DC = 61.5%
P
P
P
P
Total LT3580 power dissipation (P
T
Base Drive Loss (AC): P
Base Drive Loss (DC): P
Input Power Loss: P
Switch I
Average Switch Current: I
SW
J
SW
BAC
BDC
INP
SW
is calculated above.
= T
JA
= 1.36A
= 228mW
= switch resistance (typically 200mΩ at 1.5A)
= 35mW
J
= 270mW
= 84mW
A
= 43°C/W for the 3mm × 3mm DFN package and
= junction temperature, T
+ θ
2
R Loss: P
JA
• P
TOT
D
SW
= 0.5V:
INP
= (DC)(I
BAC
BDC
= 7mA(V
SW
IN
= 13n(I
=
=
(V
= 5V, V
A
SW
V
IN
= ambient tempera-
TOT
IN
OUT
)
)(I
V
2
SW
)
) = 617mW
IN
(R
50
SW
OUT
•I
•
SW
)(V
OUT
)(DC)
= 12V, I
OUT
)
)(f)
OUT
V
While initially powering a switching converter application,
the V
cause excessive inrush currents in the passive components
of the converter. This can lead to current and/or voltage
overstress and may damage the passive components or
the chip. Ramp rates less than 500mV/μs, depending on
component parameters, will generally prevent these issues.
Also, be careful to avoid hotplugging. Hotplugging occurs
when an active voltage supply is “instantly” connected or
switched to the input of the converter. Hotplugging results
in very fast input ramp rates and is not recommended.
Finally, for more information, refer to Linear application
note AN88, which discusses voltage overstress that can
occur when an inductive source impedance is hotplugged
to an input pin bypassed by ceramic capacitors.
Layout Hints
As with all high frequency switchers, when considering
layout, care must be taken to achieve optimal electrical,
thermal and noise performance. One will not get adver-
tised performance with a careless layout. For maximum
effi ciency, switch rise and fall times are typically in the
5ns to 10ns range. To prevent noise, both radiated and
conducted, the high speed switching current path, shown in
Figure 8, must be kept as short as possible. This is imple-
mented in the suggested layout of a boost confi guration in
Figure 9. Shortening this path will also reduce the parasitic
trace inductance. At switch-off, this parasitic inductance
produces a fl yback spike across the LT3580 switch. When
operating at higher currents and output voltages, with poor
layout, this spike can generate voltages across the LT3580
that may exceed its absolute maximum rating. A ground
plane should also be used under the switcher circuitry to
prevent interplane coupling and overall noise.
The VC and FB components should be kept as far away
as practical from the switch node. The ground for these
components should be separated from the switch cur-
rent path. Failure to do so can result in poor stability or
subharmonic oscillation.
IN
Ramp Rate
IN
ramp rate should be limited. High V
IN
ramp rates can
3580fa