x9521v20iz-b Intersil Corporation, x9521v20iz-b Datasheet
x9521v20iz-b
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x9521v20iz-b Summary of contents
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Data Sheet Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules FEATURES • Two Digitally Controlled Potentiometers (DCP’s) —100 Tap - 10kΩ —256 Tap - 100kΩ —Non-Volatile —Write Protect Function • 2kbit EEPROM Memory with Write Protect & ...
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... X9521VIB X9521V20IZ-A (Note) X9521VZIA X9521V20IZ-B (Note) X9521VZIB NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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SCL SDA Figure 2. SCL SDA Figure 1. PRINCIPLES OF OPERATION SERIAL INTERFACE Serial Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the ...
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SCL SCL from from Master Master Data Output from Transmitter Data Output from Start Receiver Figure 3. DEVICE INTERNAL ADDRESSING Addressing Protocol Overview The user addressable internal components of the X9521 can be split up into three main parts: —Two ...
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Nonvolatile Write Acknowledge Polling After a nonvolatile write command sequence (for either the EEPROM array, the Non Volatile Memory of a DCP (NVM), or the CONSTAT Register) has been correctly issued (including the final STOP condition), the X9521 initiates an ...
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Vcc t trans 0 The data in the WCR is then decoded to select and enable one of the respective FET switches. A “make before break” sequence is used internally for the FET switches when the wiper is moved from ...
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WRITE TYPE † WT Description Select a Volatile Write operation to be performed 0 on the DCP pointed to by bits P1 and P0 Select a Nonvolatile Write operation ...
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S Signals from the Master SDA Bus Signals from the Slave ( are reserved sequences, and will result in no ACKNOWLEDGE after sending an Instruction Byte on SDA. The factory default ...
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Signals from the Master SDA Bus Signals from the Slave 2kbit EEPROM ARRAY Operations on the 2kbit EEPROM Array, consist of either byte command sequences. All operations on the EEPROM must begin with the Device Type ...
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Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11. Signals from the Master SDA Bus Signals from the Slave Figure 14. Current EEPROM Address Read Sequence EEPROM Array Read Operations Read operations are ...
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S t Signals from a the Master r t SDA Bus Signals from the Slave Figure 15. Random EEPROM Address Read Sequence Random EEPROM Read Random read operation allows the master to access ...
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CS3 CS7 CS6 CS4 CS5 BL1 BL0 NV NV Bit(s) Description CS7 - CS5 Always “0”(RESERVED) BL1 - BL0 Sets the Block Lock partition RWEL Register Write Enable Latch bit WEL Write Enable Latch bit CS0 Always ...
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SCL SDA SLAVE ADDRESS BYTE T Figure 18. CONSTAT Register Write Command Sequence The region of EEPROM memory which is protected / locked is determined by the combination of ...
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S t Signals from a the Master Address r t SDA Bus Signals from the Slave Figure 19. CONSTAT Register Read Command Sequence For example, a sequence of writes to the device CON- ...
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ABSOLUTE MAXIMUM RATINGS Temperature under Bias Storage Temperature Voltage on WP pin (With respect to Vss) Voltage on other pins (With respect to Vss) | Voltage Voltage D.C. Output Current (SDA) Lead Temperature ...
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TIMING DIAGRAMS Figure 22. Bus Timing t F SCL t SU:ST t HD:STA SDA IN SDA OUT Figure 23. WP Pin Timing START SCL SDA IN WP Figure 24. Write Cycle Timing SCL 8th bit of last byte SDA 16 ...
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Figure 25. DCP “Wiper Position” Timing Rwx (x = 1,2) R wx( tap position SCL SDA SLAVE ADDRESS BYTE T 17 X9521 ...
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D.C. OPERATING CHARACTERISTICS Symbol Parameter Current into V Pin CC (1) I CC1 Read memory array Write nonvolatile memory Current into V Pin CC (2) I CC2 With 2-Wire bus activity Input Leakage Current (SCL, SDA Input Leakage ...
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A.C. CHARACTERISTICS (See Figure 22, Figure 23, Figure 24) Symbol f SCL Clock Frequency SCL (5) Pulse width Suppression Time at inputs t IN (5) SCL LOW to SDA Data Out Valid t AA (5) Time the bus free before ...
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POTENTIOMETER CHARACTERISTICS Symbol Parameter R End to End Resistance Tolerance TOL V R Terminal Voltage (x = 1,2) RHx Terminal Voltage (x = 1,2) RLx L P (1) Power Rating ( DCP Wiper Resistance W ...
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APPENDIX 1 DCP1 (100 Tap) Tap position to Data Byte translation Table Tap Position Decimal ...
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APPENDIX 2 DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1) unsigned DCP1_TAP_Position(int tap_pos) { int block; int i; int offset; int wcr_val; offset= 0; block = tap_pos / 25; if (block < 0) return ((unsigned)0); ...
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APPENDIX 2 DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2) unsigned DCP100_TAP_Position(int tap_pos optional range checking */ if (tap_pos < 0) return ((unsigned)0); else if (tap_pos >99) return ((unsigned) 96); /* 100 Tap ...
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... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...