hpc36164 National Semiconductor Corporation, hpc36164 Datasheet - Page 12

• Manufacturer Part Number: hpc36164
• Description: High-performance Microcontroller With A/d
• Manufacturer: National Semiconductor Corporation

Pin Descriptions
The HPC46164 is available only in an 80-pin PQFP pack-
age
I O PORTS
Port A is a 16-bit bidirectional I O port with a data direction
register to enable each separate pin to be individually de-
fined as an input or output When accessing external memo-
ry port A is used as the multiplexed address data bus
Port B is a 16-bit port with 12 bits of bidirectional I O similar
in structure to Port A Pins B10 B11 B12 and B15 are gen-
eral purpose outputs only in this mode Port B may also be
configured via a 16-bit function register BFUN to individually
allow each pin to have an alternate function
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 UA0
B11 WRRDY Write Ready Output for UPI Mode
B12
B13 TS2
B14 TS3
B15 RDRDY Read Ready Output for UPI Mode
When accessing external memory four bits of port B are
used as follows
B10 ALE
B11 WR
B12 HBE
B15 RD
Port I is an 8-bit input port that can be read as general
purpose inputs and is also used for the following functions
I0
I1
I2
I3
I4
I5
I6
I7
TDX
CKX
T2IO
T3IO
SO
SK
HLDA
TS0
TS1
NMI
INT2
INT3
INT4
SI
RDX
UART Data Output
UART Clock (Input or Output)
Timer2 I O Pin
Timer3 I O Pin
MICROWIRE PLUS Output
MICROWIRE PLUS Clock (Input or Output)
Hold Acknowledge Output
Timer Synchronous Output
Timer Synchronous Output
Address 0 Input for UPI Mode
Timer Synchronous Output
Timer Synchronous Output
Address Latch Enable Output
Write Output
High Byte Enable Output Input
(sampled at reset)
Read Output
Nonmaskable Interrupt Input
Maskable Interrupt Input Capture URD
Maskable Interrupt Input Capture UWR
Maskable Interrupt Input Capture
MICROWIRE PLUS Data Input
UART Data Input
External Start A D Conversion
12
Port D is an 8-bit input port that can be used as general
purpose digital inputs or as analog channel inputs for the
A D converter These functions of Port D are mutually ex-
clusive and under the control of software
Port P is a 4-bit output port that can be used as general
purpose data or selected to be controlled by timers 4
through 7 in order to generate frequency duty cycle and
pulse width modulated outputs
POWER SUPPLY PINS
V
V
GND
DGND
Note There are two electrically connected V
CLOCK PINS
CKI
CKO
Pins CKI and CKO are usually connected across an external
crystal
CK2
OTHER PINS
WO
ST1
ST2
RESET
RDY HLD
V
EXM
EI
EXUI
CC1
CC2
REF
DGND are electrically isolated Both V
must be used
and
Positive Power Supply
Ground for On-Chip Logic
Ground for Output Buffers
The Chip System Clock Input
The Chip System Clock Output (inversion of
CKI)
Clock Output (CKI divided by 2)
This is an active low open drain output that
signals an illegal situation has been detected
by the WATCHDOG logic
Bus Cycle Status Output indicates first op-
code fetch
Bus Cycle Status Output indicates machine
states (skip interrupt and first instruction cy-
cle)
Active low input that forces the chip to restart
and sets the ports in a TRI-STATE mode
Selected by a software bit It’s either a
READY input to extend the bus cycle for slow-
er memories or a HOLD request input to put
the bus in a high impedance state for DMA
purposes
A D converter reference voltage input
External memory enable (active high) disables
internal ROM and maps it to external memory
External
FFF1 FFF0 (Rising falling edge or high low
level sensitive) Alternately can be configured
as 4th input capture
External active low interrupt which is internally
OR’ed with the UART interrupt with vector ad-
dress FFF3 FFF2
interrupt
CC
CC
with
pins on the chip GND and
pins and both ground pins
vector
address