hip1011b Intersil Corporation, hip1011b Datasheet - Page 8

• Manufacturer Part Number: hip1011b
• Description: Pci Hot Plug Controller
• Manufacturer: Intersil Corporation

HIP1011 Split Load Application
All of the members of the HIP1011 family, including the
HIP1011B, can be used in an application where two
electrically isolated loads are to be powered from a common
bus. This may occur in a system that has a power
management feature controlled by a system controller IC
invoking a sleep or standby state. Thus one load can be shut
down while maintaining power to a second isolated circuit.
The circuit shown in Figure 7 shows the external FETs, and
sense resistor configuration for the 3.3V and/or 5V load that
has such a requirement. The HIP1011 is represented by pin
names in rectangles. Q1 and Q2 are the N-Channel FETs for
each load on this rail, these are sized appropriately for each
load. R1 and R2 are needed to pull down the supply slot pins
or load when slot power is disabled as the load discharge
FETs (Q3) on the VISEN pins are no longer attached to the
load. When power is turned off to the load these (~100Ω)
FETs turn on, thus some low current, (10mA) continues to
be drawn from the supply in addition to the sleep load
current resulting in a 4
SYSTEM POWER MGT CONTROLLER
PWRON
3V5VG
VISEN
VS
FIGURE 7. SPLIT LOAD CIRCUIT
Q1
Q3
V
o
SUPPLY
C die temperature rise.
Q2
R
SENSE
8
R1
R2
TO SLEEP LOAD
TO FULL LOAD
HIP1011B
HIP1011 High Power Circuit
Instances occur when a noncompliant card is designed for
use in a PCI environment. Although the HIP1011 family has
proven to be very design flexible, controlling high power
+12V supplies requires special attention. This is due to
thermal considerations that limit the integrated power
device on the +12V supply to about 1.5A. To address this
an external add on circuit as shown in Figure 8 enables the
designer to add the OC monitoring and control of a high
power +12V supply in addition to the 3 other power
supplies. The HIP1011 is represented by pin names in
rectangles.
This circuit primarily requires that an external P-Channel
MOSFET be connected in parallel to the internal HIP1011
PMOS device and that the discrete device have a much
lower r
to carry the majority of the current load. By monitoring the
voltage across the sense resistor carrying the combined
load current of both the internal and external FETs and by
using a comparator with a common mode input voltage
range to the positive rail and a low input voltage threshold
offset to reduce distribution losses, a high precision OC
detector can be designed to control a much higher current
load than can be tolerated by the HIP1011.
An alternative circuit for moderate current levels where both
accuracy and cost are lowered can be accomplished by a
single external P-Channel MOSFET in parallel with the
internal P-Channel MOSFET. For example, if 2X the OC level
is desired a 0.3Ω r
thus approximately doubling the +12 IOUT before latch-off.
IOC
FET/r
12VG
12VO
TOTAL
DS(ON)
DS(ON)
TO +12V LOAD
Q1
= IOC
FIGURE 8. HIGH POWER +12V CIRCUIT
12VIN
of external FET).
value than the internal PMOS device in order
R
INTERNAL
SENSE
DS(ON)
R1
P-Channel MOSFET can be used
(1 + r
+
-
12VIN
DS(ON)
R2
of internal
R3
November 18, 2004
FLTN
FN4640.5
Q2